IP Library › Granted Patent US 10,553,727
Granted Patent B2
US 10,553,727 · App. 15/858,679 · Granted Feb 4, 2020

Thin film transistor, method of manufacturing the same, and organic light emitting display device including the same

Inventors: JongUk Bae (Seoul, KR); YongHo Jang (Goyang-si, KR)
Assignee: LG Display Co., Ltd.
H01L29/7869H01L27/3248H01L27/3276H01L29/66969H01L29/78648
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Quick Facts
Patent No.
US 10,553,727
App. No.
15/858,679
Granted
Feb 4, 2020
Kind
B2
Abstract

Disclosed are a thin film transistor, a method of manufacturing the same, and an organic light emitting display device including the same, in which a driving stability of a driving transistor is enhanced even without connecting a source electrode to a bottom gate electrode of the driving transistor. The film transistor includes a N-type semiconductor layer, a P-type semiconductor layer on the N-type semiconductor layer, a first gate electrode on the P-type semiconductor layer, a gate insulation layer between the first gate electrode and the P-type semiconductor layer, a first source electrode connected to a first side of the P-type semiconductor layer, and a first drain electrode connected to a second side of the P-type semiconductor layer.

Claims (72)

1. A thin film transistor comprising:

an N-type semiconductor layer;

a P-type semiconductor layer on the N-type semiconductor layer;

a first gate electrode over the P-type semiconductor layer;

a gate insulation layer between the first gate electrode and the P-type semiconductor layer;

a first source electrode connected to a first side of the P-type semiconductor layer; and

a first drain electrode connected to a second side of the P-type semiconductor layer.

2. The thin film transistor of claim 1 , wherein when, a threshold voltage of the N-type semiconductor layer satisfies where

Vth

N

⁢

⁢

1

>

DV

2

,

Vth N1 is the threshold voltage of the N-type semiconductor layer is and DV is a drain voltage applied to the first drain electrode.

3. The thin film transistor of claim 1 , wherein

the first source electrode includes a first source electrode layer contacting the P-type semiconductor layer and having a P-type semiconductor characteristic, and a second source electrode layer disposed on the first source electrode layer, and

the first drain electrode includes a first drain electrode layer contacting the P-type semiconductor layer and having the P-type semiconductor characteristic, and a second drain electrode layer disposed on the first drain electrode layer.

4. The thin film transistor of claim 3 , wherein the P-type semiconductor layer, the first source electrode layer, and the first drain electrode layer are formed of the same material.

5. The thin film transistor of claim 1 , wherein the P-type semiconductor layer has a thickness thinner than a thickness of the N-type semiconductor layer.

6. The thin film transistor of claim 1 , wherein the N-type semiconductor layer is an N-type oxide semiconductor layer, and the P-type semiconductor layer is a P-type oxide semiconductor layer.

7. The thin film transistor of claim 6 , wherein the P-type semiconductor layer includes Cu 2 O.

8. A method of manufacturing a thin film transistor, the method comprising:

forming a first N-type semiconductor layer and a P-type semiconductor layer of a first thin film transistor and a second N-type semiconductor layer of a second thin film transistor, on a first gate insulation layer;

forming a second gate insulation layer on the P-type semiconductor layer and forming the second gate insulation on the second N-type semiconductor layer;

forming a first gate electrode overlapping the P-type semiconductor layer on the second gate insulation layer and a second gate electrode overlapping the second N-type semiconductor layer on the second gate insulation layer;

forming an interlayer dielectric on the first gate electrode and the second gate electrode;

forming first and second contact holes exposing a portion of the P-type semiconductor layer to pass through the interlayer dielectric, and third and fourth contact holes exposing a portion of the second N-type semiconductor layer; and

forming a first source electrode connected to the P-type semiconductor layer through the first contact hole, a first drain electrode connected to the P-type semiconductor layer through the second contact hole, a second source electrode connected to the second N-type semiconductor layer through the third contact hole, and a second drain electrode connected to the second N-type semiconductor layer through the fourth contact hole, on the interlayer dielectric.

9. The method of claim 8 , wherein a threshold voltage of the first N-type semiconductor layer satisfies

Vth

N

⁢

⁢

1

>

DV

2

,

where Vth N1 is the threshold voltage of the first N-type semiconductor layer and DV is a drain voltage applied to the first drain electrode.

10. The method of claim 8 , wherein the P-type semiconductor layer has a thickness thinner than a thickness of the first N-type semiconductor layer.

11. The method of claim 8 , wherein the first N-type semiconductor layer and the second N-type semiconductor layer are an N-type oxide semiconductor layer, and the P-type semiconductor layer is a P-type oxide semiconductor layer.

12. The thin film transistor of claim 11 , wherein the P-type semiconductor layer includes Cu 2 O.

13. An organic light emitting display device comprising:

a pixel including an organic light emitting diode, a first thin film transistor, and a second thin film transistor, and connected to a scan line and a data line,

wherein the first thin film transistor has a first N-type semiconductor layer and a P-type semiconductor layer is disposed on the first N-type semiconductor layer, and the second thin film transistor has a second N-type semiconductor layer.

14. The organic light emitting display device of claim 13 , wherein a threshold voltage of the first N-type semiconductor layer satisfies

Vth

N

⁢

⁢

1

>

DV

2

,

where Vth N1 is a threshold voltage of the first N-type semiconductor layer and DV is a source voltage.

15. The organic light emitting display device of claim 13 , wherein the first thin film transistor further comprises:

a first gate electrode on the P-type semiconductor layer;

a gate insulation layer between the first gate electrode and the P-type semiconductor layer;

a first source electrode connected to a first side of the P-type semiconductor layer; and

a first drain electrode connected to a second side of the P-type semiconductor layer.

16. The organic light emitting display device of claim 15 , wherein

each of the first and second source electrodes comprises a first source electrode layer contacting the P-type semiconductor layer and having a P-type semiconductor characteristic, and a second source electrode layer disposed on the first source electrode layer, and

each of the first and second drain electrodes comprises a first drain electrode layer contacting the P-type semiconductor layer and having the P-type semiconductor characteristic, and a second drain electrode layer disposed on the first drain electrode layer.

17. The organic light emitting display device of claim 16 , wherein the P-type semiconductor layer, the first source electrode layer, and the first drain electrode layer are formed of the same material.

18. The organic light emitting display device of claim 13 , wherein a thickness of the P-type semiconductor layer is thinner than a thickness of the first N-type semiconductor layer.

19. The organic light emitting display device of claim 13 , wherein each of the first and second N-type semiconductor layers is an N-type oxide semiconductor layer, and the first P-type semiconductor layer is a P-type oxide semiconductor layer.

20. The organic light emitting display device of claim 19 , wherein the P-type semiconductor layer includes Cu 2 O.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2018
From: BAE, JONGUK; JANG, YONGHO
To: LG DISPLAY CO., LTD.
Reel/Frame 044832/0645 →
Priority Claims (1)
KR 10-2016-0184043 · Dec 30, 2016 · national
Continuity (1)
Related Publication 20180190824A1 · Jul 5, 2018