Method for obtaining phase detection signal in clock recovery circuit and phase detector
Embodiments of this application provide a method for obtaining a phase detection signal in a clock recovery circuit and a phase detector, configured to obtain a correct phase detection signal. A phase detector obtains sampling sequences sent by an analog to digital converter ADC, where the sampling sequences are obtained by the ADC by sampling, an electrical signal received by the ADC, and the electrical signal carries a pre-configured training sequence; the phase detector calculates a correlation between the sampling sequences and a comparison sequence, to determine a first location and a second location, where the first location and the second location are locations of a starting point of the training sequence in the sampling sequences; and the phase detector obtains a phase detection signal based on a difference parameter of the first location and the second location.
1. A method for obtaining a phase detection signal in a clock recovery circuit, the method comprising:
receiving, by a phase detector, sampling sequences sent by an analog to digital converter (ADC), wherein the sampling sequences are obtained by the ADC by sampling, based on an actual sampling rate, an electrical signal received by the ADC, and the electrical signal carries a pre-configured training sequence;
calculating, by the phase detector, a correlation between the sampling sequences and a comparison sequence, to determine a first location and a second location, wherein the first location and the second location are locations of a starting point of the training sequence in the sampling sequences, there is a difference of M1 training sequence periods (wherein M1 is a positive integer) between the first location and the second location in the sampling sequences, and the comparison sequence is generated by the phase detector based on the training sequence and a target sampling rate of the ADC; and
obtaining, by the phase detector, a phase detection signal based on a difference parameter of the first location and the second location.
2. The method according to claim 1 , wherein calculating, by the phase detector, a correlation between the sampling sequences and a comparison sequence, to determine a first location and a second location comprises:
calculating, by the phase detector, a correlation between the comparison sequence and the sampling sequence based on a first formula, to determine the first location of the starting point of the training sequence; and
calculating, by the phase detector, a correlation between the comparison sequence and the sampling sequence based on a second formula, to determine the second location of the starting point of the training sequence.
3. The method according to claim 2 , wherein:
the first formula is:
C n 0 [ i ]=Σ k 2 =0 k 2 =m−1 Σ k 1 =0 k 1 =N p −1 r [ n 0 +k 2 *N p +k 1 ] P *[mod( k 1 +i− 1, N p )+1];
the second formula is:
C n 1 [ i ]=Σ k 2 =0 k 2 =m−1 Σ k 1 =0 k 1 =N p −1 r [ n 1 +k 2 *N p +k 1 ] P *[mod( k 1 +i− 1, N p )+1];
the first location is:
a data sequence number corresponding to i in max(C n 0 [i], i=1, 2, . . . , N p ); and
the second location is:
a data sequence number corresponding to i in max(C n 1 [i], i=1, 2, . . . , N p ), where
r is the sampling sequence, P is the comparison sequence, n 0 is the starting point of the sampling sequence, N p is a comparison sequence period, i is a data sequence number of the sampling sequence, n 1 is the starting point of the sampling sequence after a delay of K1 N p s is performed on n 0 (where K1 is a positive integer), and m is a quantity of preselected comparison sequence periods.
4. The method according to claim 2 , wherein:
the first formula is:
C n 0 [ i ]=Σ k 2 =0 k 2 =m−1 |Σ k 1 =0 k 1 =N p −1 r [ n 0 +k 2 *N p +k 1 ] P *[mod( k 1 +i− 1, N p )+1]|;
the second formula is:
C n 1 [ i ]=Σ k 2 =0 k 2 =m−1 |Σ k 1 =0 k 1 =N p −1 r [ n 1 +k 2 *N p +k 1 ] P *[mod( k 1 +i− 1, N p )+1]|;
the first location is:
a data sequence number corresponding to i in max(C n 0 [i], i=1, 2, . . . , N p ); and
the second location is:
a data sequence number corresponding to i in max(C n 1 [i], i=1, 2, . . . , N p ), where
r is the sampling sequence, P is the comparison sequence, n 0 is the starting point of the sampling sequence, N p is a comparison sequence period, i is a data sequence number of the sampling sequence, n 1 is the starting point of the sampling sequence after a delay of K1 N p s is performed on n 0 (where K1 is a positive integer), and m is a quantity of preselected comparison sequence periods.
5. The method according to claim 1 , wherein after obtaining, by the phase detector, a phase detection signal based on a difference parameter of the first location and the second location, the method further comprises:
sending, by the phase detector, the phase detection signal to the ADC to enable the ADC to adjust the actual sampling rate based on the phase detection signal.
6. The method according to claim 1 , wherein obtaining, by the phase detector, a phase detection signal based on a difference parameter of the first location and the second location comprises:
comparing, by the phase detector, the first location with the second location to obtain the difference parameter;
when the difference parameter indicates that the first location is greater than the second location, determining, by the phase detector, that the phase detection signal indicates the actual sampling rate is less than the target sampling rate;
when the difference parameter indicates that the first location is less than the second location, determining, by the phase detector, that the phase detection signal indicates the actual sampling rate is greater than the target sampling rate; and
when the difference parameter indicates that the first location is equal to the second location, determining, by the phase detector, that the phase detection signal indicates the actual sampling rate is equal to the target sampling rate.
7. A phase detector, comprising:
a receiver, configured to receive sampling sequences sent by an analog to digital converter (ADC), wherein the sampling sequences are obtained by the ADC by sampling, based on an actual sampling rate, an electrical signal received by the ADC, and the electrical signal carries a pre-configured training sequence; and
a processor, configured to:
calculate a correlation between the sampling sequences and a comparison sequence, to determine a first location and a second location, wherein the first location and the second location are locations of a starting point of the training sequence in the sampling sequences, there is a difference of M1 training sequence periods (wherein M1 is a positive integer) between the first location and the second location in the sampling sequences, and the comparison sequence is generated by the phase detector based on the training sequence and a target sampling rate of the ADC, and
obtain a phase detection signal based on a difference parameter the first location and the second location.
8. The phase detector according to claim 7 , wherein the processor is further configured to:
calculate a correlation between the comparison sequence and the sampling sequence based on a first formula, to determine the first location of the starting point of the training sequence; and
calculate a correlation between the comparison sequence and the sampling sequence based on a second formula, to determine the second location of the starting point of the training sequence.
9. The phase detector according to claim 8 , wherein the first formula is:
C n 0 [ i ]=Σ k 2 =0 k 2 =m−1 Σ k 1 =0 k 1 =N p −1 r [ n 0 +k 2 *N p +k 1 ] P *[mod( k 1 +i− 1, N p )+1];
the second formula is:
C n 1 [ i ]=Σ k 2 =0 k 2 =m−1 Σ k 1 =0 k 1 =N p −1 r [ n 1 +k 2 *N p +k 1 ] P *[mod( k 1 +i− 1, N p )+1];
the first location is:
a data sequence number corresponding to i in max(C n 0 [i], i=1, 2, . . . , N p ); and
the second location is:
a data sequence number corresponding to i in max(C n 1 [i], i=1, 2, . . . , N p ), where
r is the sampling sequence, P is the comparison sequence, n 0 is the starting point of the sampling sequence, N p is a comparison sequence period, i is a data sequence number of the sampling sequence, n 1 is the starting point of the sampling sequence after a delay of K1 N p s is performed on n 0 (where K1 is a positive integer), and m is a quantity of preselected comparison sequence periods.
10. The phase detector according to claim 8 , wherein the first formula is:
C n 0 [ i ]=Σ k 2 =0 k 2 =m−1 |Σ k 1 =0 k 1 =N p −1 r [ n 0 +k 2 *N p +k 1 ] P *[mod( k 1 +i− 1, N p )+1]|;
the second formula is:
C n 1 [ i ]=Σ k 2 =0 k 2 =m−1 |Σ k 1 =0 k 1 =N p −1 r [ n 1 +k 2 *N p +k 1 ] P *[mod( k 1 +i− 1, N p )+1]|;
the first location is:
a data sequence number corresponding to i in max(C n 0 [i], i=1, 2, . . . , N p ); and
the second location is:
a data sequence number corresponding to i in max(C n 1 [i], i=1, 2, . . . , N p ), where
r is the sampling sequence, P is the comparison sequence, n 0 is the starting point of the sampling sequence, N p is a comparison sequence period, i is a data sequence number of the sampling sequence, n 1 is the starting point of the sampling sequence after a delay of K1 N p s is performed on n 0 (where K1 is a positive integer), and m is a quantity of preselected comparison sequence periods.
11. The phase detector according to claim 7 , wherein the phase detector further comprises:
a transmitter configured to send the phase detection signal to the ADC to enable the ADC to adjust the actual sampling rate based on the phase detection signal.
12. The phase detector according to claim 7 , wherein the processor is further configured to:
compare the first location with the second location to obtain the difference parameter; and
when the difference parameter indicates that the first location is greater than the second location, determine that the phase detection signal indicates the actual sampling rate is less than the target sampling rate;
when the difference parameter indicates that the first location is less than the second location, determine that the phase detection signal indicates the actual sampling rate is greater than the target sampling rate; or
when the difference parameter indicates that the first location is equal to the second location, determine that the phase detection signal indicates the actual sampling rate is equal to the target sampling rate.
13. A phase detector, comprising:
a bus;
a transceiver coupled to the bus and configured to:
receiving sampling sequences sent by an analog to digital converter ADC, wherein the sampling sequences are obtained by the ADC by sampling, based on an actual sampling rate, an electrical signal received by the ADC, and the electrical signal carries a pre-configured training sequence; and
a processor coupled to the bus and configured to:
calculate a correlation between the sampling sequences and a comparison sequence, to determine a first location and a second location, wherein the first location and the second location are locations of a starting point of the training sequence in the sampling sequences, there is a difference of M1 training sequence periods (wherein M1 is a positive integer) between the first location and the second location in the sampling sequences, and the comparison sequence is generated by the phase detector based on the training sequence and a target sampling rate of the ADC, and
obtain a phase detection signal based on a difference parameter of the first location and the second location.