Three-dimensional vertical one-time-programmable memory comprising Schottky diodes
View Patent ↗The present invention discloses a three-dimensional vertical read-only memory (3D-OTP V ) comprising Schottky diodes. It comprises a plurality of vertical OTP strings formed side-by-side on a substrate circuit. Each OTP string is vertical to the substrate and comprises a plurality of vertically stacked OTP cells. Each OTP cell comprises an antifuse layer. A plurality of Schottky diodes are formed between the horizontal address lines and the vertical address lines.
1. A three-dimensional vertical one-time-programmable memory (3D-OTP V ), comprising:
a semiconductor substrate comprising a substrate circuit;
a plurality of vertically stacked horizontal address lines above said semiconductor circuit;
a plurality of memory holes through said horizontal address lines;
an antifuse layer on and in contact with the sidewalls of said memory holes, wherein said antifuse layer is irreversibly switched from a high-resistance state to a low-resistance state during programming;
a plurality of vertical address lines in said memory holes and in contact with said antifuse layer;
a plurality of OTP cells at the intersections of said horizontal and vertical address lines, wherein said horizontal and vertical address lines form a Schottky diode at a selected one of said OTP cells whose antifuse layer is in said low-resistance state;
wherein said horizontal and vertical address lines are separated by said antifuse layer only.
2. The 3D-OTP V according to claim 1 , wherein said horizontal address lines comprise at least a metallic material, said vertical address lines comprise at least a doped semiconductor material.
3. The 3D-OTP V according to claim 1 , wherein said horizontal address lines comprise at least a doped semiconductor material, said vertical address lines comprise at least a metallic material.
4. The 3D-OTP V according to claim 1 , wherein said plurality of OTP cells form a vertical OTP string.
5. The 3D-OTP V according to claim 4 , further comprising a vertical transistor coupled to said OTP string.
6. The 3D-OTP V according to claim 5 , wherein said vertical transistor is formed in a first portion of selected one of said memory holes, and said OTP string is formed in a second portion of said selected one of said memory holes.
7. The 3D-OTP V according to claim 1 , wherein said OTP cells have more than two states, the OTP cells in different states having different resistance values.
8. A three-dimensional vertical one-time-programmable memory (3D-OTP V ), comprising:
a semiconductor substrate comprising a substrate circuit;
a plurality of vertically stacked horizontal address lines above said semiconductor circuit, said horizontal address lines comprising at least a metallic material;
a plurality of memory holes through said horizontal address lines;
an antifuse layer on and in contact with the sidewalls of said memory holes, wherein said antifuse layer is irreversibly switched from a high-resistance state to a low-resistance state during programming;
a plurality of vertical address lines in said memory holes and in contact with said antifuse layer, said vertical address lines comprising at least a doped semiconductor material;
a plurality of OTP cells at the intersections of said horizontal and vertical address lines, wherein said horizontal and vertical address lines form a Schottky diode at a selected one of said OTP cells whose antifuse layer is in said low-resistance state;
wherein said horizontal and vertical address lines are separated by said antifuse layer only.
9. The 3D-OTP V according to claim 8 , wherein a vertical transistor is formed in a first portion of selected one of said memory holes, and said plurality of OTP cells are formed in a second portion of said selected one of said memory holes.
10. The 3D-OTP V according to claim 8 , wherein said OTP cells have more than two states, the OTP cells in different states having different resistance values.
11. A three-dimensional vertical one-time-programmable memory (3D-OTP V ), comprising:
a semiconductor substrate comprising a substrate circuit;
a plurality of vertically stacked horizontal address lines above said semiconductor circuit, said horizontal address lines comprising at least a doped semiconductor material;
a plurality of memory holes through said horizontal address lines;
an antifuse layer on and in contact with the sidewalls of said memory holes, wherein said antifuse layer is irreversibly switched from a high-resistance state to a low-resistance state during programming;
a plurality of vertical address lines in said memory holes and in contact with said antifuse layer, said vertical address lines comprising at least a metallic material;
a plurality of OTP cells at the intersections of said horizontal and vertical address lines, wherein said horizontal and vertical address lines form a Schottky diode at a selected one of said OTP cells whose antifuse layer is in said low-resistance state;
wherein said horizontal and vertical address lines are separated by said antifuse layer only.
12. The 3D-OTP V according to claim 11 , wherein a vertical transistor is formed in a first portion of selected one of said memory holes, and said plurality of OTP cells are formed in a second portion of said selected one of said memory holes.
13. The 3D-OTP V according to claim 11 , wherein said OTP cells have more than two states, the OTP cells in different states having different resistance values.