Stacked silicon nanotubes
Embodiments of the present invention are directed to a method that incorporates a germanium pull-out process to form semiconductor structures having stacked silicon nanotubes. In a non-limiting embodiment of the invention, a sacrificial layer is formed over a substrate. The sacrificial layer includes a first type of semiconductor material. A pull-out layer is formed on the sacrificial layer. The first type of semiconductor material from the sacrificial layer is removed to form a silicon-rich layer on a surface of the sacrificial layer. The sacrificial layer can be removed such that the silicon-rich layer defines a silicon nanotube.
1. A method for forming a semiconductor device, the method comprising: forming one or more stacked nanowires comprising a sacrificial material over a substrate, the sacrificial material comprising a first type of semiconductor material; forming a pull-out layer around each of the one or more stacked nanowires; reacting the pull-out layer with the first type of semiconductor material to form a silicon-rich layer on a surface of each of the one or more stacked nanowires; and removing the sacrificial material to define one or more hollow nanotubes comprising the silicon-rich layer.
2. The method of claim 1 further comprising removing portions of the silicon-rich layer such that remaining portions of the silicon-rich layer define a silicon nanotube.
3. The method of claim 1 , wherein the pull-out layer comprises germanium oxide and the first type of semiconductor material comprises germanium.
4. The method of claim 3 , further comprising annealing the semiconductor device at a temperature of at least 900 degrees Celsius.
5. The method of claim 4 , wherein annealing the semiconductor device removes germanium from the sacrificial layer according to the formula:
Ge+GeO 2 −>2GeO. (I)
6. The method of claim 4 , wherein annealing the semiconductor device comprises a temperature spike anneal.
7. The method of claim 1 , wherein the sacrificial layer comprises silicon germanium having a germanium concentration of about 40 percent to about 50 percent.
8. A method for forming a semiconductor device, the method comprising:
forming a semiconductor layer on a substrate;
forming a sacrificial layer on the semiconductor layer, the sacrificial layer comprising silicon germanium;
patterning the semiconductor layer and the sacrificial layer into one or more fins in a first region of the substrate;
removing portions of the semiconductor layer in the first region such that a portion of the sacrificial layer in the first region defines a nanowire;
forming a pull-out layer around the nanowire in the first region;
annealing the semiconductor device to remove germanium from a surface of the nanowire such that the surface of the nanowire becomes silicon-rich; and
removing the sacrificial layer such that the silicon-rich surface remains and defines a hollow silicon nanotube.
9. The method of claim 8 , wherein the pull-out layer comprises germanium oxide.
10. The method of claim 9 , wherein annealing the semiconductor device causes germanium in the sacrificial layer to react with germanium oxide in the pull-out layer according to the formula:
Ge+GeO 2 −>2GeO. (I)
11. The method of claim 8 further comprising filling the hollow silicon nanotube with a dielectric core.
12. The method of claim 8 , wherein the semiconductor device is annealed at a temperature of at least 900 degrees Celsius.
13. The method of claim 8 , wherein annealing the semiconductor device comprises a high temperature spike anneal.
14. The method of claim 8 , wherein the sacrificial layer comprises a germanium concentration of about 40 percent to about 50 percent.