Impedance-based physical unclonable function
According to various aspects, systems and methods for providing a soft-decoding physical unclonable function are provided. According to one embodiment, PUF circuitry includes circuit elements with impedance values that are used to generate a PUF value. For example, one or more resistors may be connected to a voltage source. The resistors may generate a resulting voltage signal that is measured and indicates a ratio of the impedance values of the resistors. Due to manufacturing variations, each impedance value may be unique, such that the impedance values may be used to provide a unique number sequence. Each ratio value may be converted into a single bit or multi-bit digital value through digitization, for example with a comparator and/or an analog to digital converter, and the series of digital values may represent or be used to generate a unique number sequence.
1. An apparatus for providing an impedance based physically unclonable function (PUF), comprising:
a first pair of resistors electrically connected in a first current path, the first pair of resistors having a first impedance ratio;
a second pair of resistors electrically connected in a second current path, the second pair of resistors having a second impedance ratio;
an analog-to-digital converter (ADC), configured to generate a plurality of bits based on:
a first voltage signal from the first current path that indicates the first impedance ratio; and
a second voltage signal from the second current path that indicates the second impedance ratio; and
processing circuitry configured to generate a PUF value based on the plurality of bits.
2. The apparatus of claim 1 , wherein the ADC is further configured to generate the plurality of bits based on a first plurality of bits obtained from the first voltage signal and a second plurality of bits obtained from the second voltage signal.
3. The apparatus of claim 1 , further comprising a demultiplexer configured to: connect one of the first pair of resistors and the second pair of resistors to a voltage source.
4. The apparatus of claim 2 , wherein the processing circuitry is configured to generate the PUF value by concatenating the first plurality of bits and the second plurality of bits.
5. The apparatus of claim 1 , wherein the processing circuitry is configured to generate the PUF value by selecting a portion of the plurality of bits.
6. The apparatus of claim 1 , wherein at least one of the first pair of resistors and the second resistor pair of resistors is selected from a plurality of pairs of resistors.
7. The apparatus of claim 1 , wherein the processing circuitry is further configured to select, based on the plurality of bits, an additional pair of resistors having an additional impedance ratio; and the ADC is further configured to generate an additional plurality of bits representing an additional voltage signal that indicates the additional impedance ratio.
8. The apparatus of claim 7 , wherein a first resistor of the first pair of resistors comprises resistive material including a kerf.
9. The apparatus of claim 1 , wherein a resistor from the first and second pairs of resistors is a trimmed resistor.
10. The apparatus of claim 9 , wherein the trimmed resistor is configured to encode a predetermined value in an impedance value of the trimmed resistor.
11. A method for providing an impedance based physically unclonable function (PUF), comprising:
providing a supply voltage to:
a first pair of resistors electrically connected in a first current path, the first pair of resistors having a first impedance ratio; and
a second pair of resistors electrically connected in a second current path, the second pair of resistors having a second impedance ratio;
generating, using an analog-to-digital converter, a plurality of bits based on:
a first voltage signal from the first current path that indicates the first impedance ratio; and
a second voltage signal from the second current path that indicates the second impedance ratio; and
generating a PUF value based on the plurality of bits.
12. The method of claim 11 , further comprising generating the plurality of bits based on a first plurality of bits obtained from the first voltage signal and a second plurality of bits obtained from the second voltage signal.
13. The method of claim 12 , wherein generating the PUF value comprises concatenating the first plurality of bits and the second plurality of bits.
14. The method of claim 11 , further comprising providing, using a demultiplexer, the supply voltage to one of the first pair of resistors and the second pair of resistors.
15. The method of claim 11 , wherein generating the PUF value comprises selecting a portion of the plurality of bits.
16. The method of claim 11 , further comprising selecting at least one of the first pair of resistors and the second pair of resistors from a plurality of pairs of resistors.
17. The method of claim 11 , further comprising:
selecting, based on the plurality of bits, an additional pair of resistors having an additional impedance ratio; and
generating an additional plurality of bits representing an additional voltage signal that indicates the additional impedance ratio.
18. The method of claim 11 , wherein a resistor from the first and second pairs of resistors is a trimmed resistor.
19. The method of claim 18 , further comprising encoding a predetermined value in an impedance value of the trimmed resistor.
20. A system for providing an impedance based physically unclonable function (PUF), comprising:
a processor package comprising:
a first resistor pair having a first impedance ratio;
a second resistor pair having a second impedance ratio;
an analog-to-digital converter (ADC) electrically connected to the first resistor pair and the second resistor pair, wherein the ADC is configured to generate one or more bits that represent a difference between a voltage signal that indicates the first impedance ratio and a voltage signal that indicates the second impedance ratio; and
processing circuitry configured to generate a PUF value based on of the one or more bits.