Self-aligned nanotips with tapered vertical sidewalls

1. A method of forming a semiconductor structure, comprising:

forming a substrate;

forming an anchor layer; and

forming one or more self-aligned nanotip pillar pairs disposed vertically between the substrate and the anchor layer;

wherein a given one of the nanotip pillar pairs comprises a bottom nanotip pillar and a top nanotip pillar, the bottom nanotip pillar comprising a base portion disposed on a top surface of the substrate and the top nanotip pillar comprising a base portion disposed in the anchor layer;

wherein the bottom nanotip pillar and the top nanotip pillar comprise sidewalls that taper to points as distance from the respective base portions increases; and

wherein the given nanotip pillar pair comprises a graded concentration of a semiconductor material which decreases in concentration as distance from a vertical center of the given nanotip pillar pair increases.

2. The method of claim 1 , wherein the semiconductor material comprises germanium (Ge).

3. The method of claim 1 , wherein forming the one or more self-aligned nanotip pillar pairs comprises:

forming a film stack disposed over the top surface of the substrate, the film stack comprising the graded concentration of the semiconductor material;

patterning a hard mask disposed over a top surface of the film stack; and

performing sidewall image transfer to form one or more pillars from the film stack.

4. The method of claim 3 , further comprising:

filling an oxide disposed over the top surface of the substrate and over the one or more pillars; and

recessing the oxide to expose sidewalls of at least a portion of the film stack of the one or more pillars.

5. The method of claim 4 , wherein forming the anchor layer comprises depositing a nitride on the exposed sidewalls of the one or more pillars to form nitride rings around each of the one or more pillars, wherein the nitride rings around closest ones of the pillars pinch off leaving gap areas among the one or more pillars.

6. The method of claim 5 , further comprising etching the nitride to expose a top surface of the oxide in the gap areas.

7. The method of claim 6 , further comprising performing a thermal oxidation.

8. The method of claim 7 , wherein a rate of oxidization of the nanotip pillar pairs is proportional to a concentration of the semiconductor material.

9. The method of claim 7 , wherein portions of the nanotip pillars with relatively higher concentration of the semiconductor material oxidize faster than portions of the nanotip pillars with relatively lower concentration of the semiconductor material.

10. The method of claim 7 , wherein the thermal oxidation forms the tapered sidewalls of the bottom nanotip pillar and the top nanotip pillar.

11. The method of claim 10 , wherein the sidewalls of the bottom nanotip pillar and the top nanotip pillar taper to respective points proximate the vertical center of the given nanotip pillar.

12. The method of claim 7 , further comprising removing the oxide prior to performing the thermal oxidation.

13. The method of claim 7 , further comprising:

removing the hard mask to expose top surfaces of the one or more nanotip pillars; and

forming epitaxial layers over the exposed top surfaces of the one or more nanotip pillars.

14. The method of claim 13 , further comprising forming at least one contact to the epitaxial layers.

15. A semiconductor structure, comprising:

a substrate;

an anchor layer; and

one or more self-aligned nanotip pillar pairs disposed vertically between the substrate and the anchor layer;

wherein a given one of the nanotip pillar pairs comprises a bottom nanotip pillar and a top nanotip pillar, the bottom nanotip pillar comprising a base portion disposed on a top surface of the substrate and the top nanotip pillar comprising a base portion disposed in the anchor layer;

wherein the bottom nanotip pillar and the top nanotip pillar comprise sidewalls that taper to points as distance from the respective base portions increases; and

wherein the given nanotip pillar pair comprises a graded concentration of a semiconductor material which decreases in concentration as distance from a vertical center of the given nanotip pillar pair increases.

16. The semiconductor structure of claim 15 , wherein the semiconductor material comprises germanium (Ge).

17. The semiconductor structure of claim 15 , wherein the base portions of the bottom nanotip pillar and the top nanotip pillar are cylindrical.

18. The semiconductor structure of claim 15 , wherein the base portions of the bottom nanotip pillar and the top nanotip pillar are rectangular or square.

19. An integrated circuit comprising:

a gas ionization sensor comprising:

a substrate;

an anchor layer; and

one or more self-aligned nanotip pillar pairs disposed vertically between the substrate and the anchor layer;

wherein a given one of the nanotip pillar pairs comprises a bottom nanotip pillar and a top nanotip pillar, the bottom nanotip pillar comprising a base portion disposed on a top surface of the substrate and the top nanotip pillar comprising a base portion disposed in the anchor layer;

wherein the bottom nanotip pillar and the top nanotip pillar comprise sidewalls that taper to points as distance from the respective base portions increases; and

wherein the given nanotip pillar pair comprises a graded concentration of a semiconductor material which decreases in concentration as distance from a vertical center of the given nanotip pillar pair increases.

20. The integrated circuit of claim 19 , wherein the semiconductor material comprises germanium (Ge).