Multi-thread processor and controlling method thereof
A multi-thread processor and a method of controlling a multi-thread processor are provided. The multi-thread processor includes at least one functional unit; a mode register; and a controller configured to control the mode register to store thread mode information corresponding to a task to be processed among a plurality of thread modes, wherein the plurality of thread modes are divided based on a size and a number of at least one thread that is concurrently processed in one of the at least one functional unit, allocate at least one thread included in the task to the at least one functional unit based on the thread mode information stored in the mode register and control the at least one functional unit to process the at least one thread.
1. A multi-thread processor, comprising:
a functional unit;
a mode register; and
a controller configured to:
control the mode register to store information about a thread mode corresponding to a task to be processed from among a plurality of thread modes, wherein the plurality of thread modes are divided based on a size and a number of a plurality of threads that is concurrently processed in the functional unit,
allocate the plurality of threads included in the task to the functional unit based on the information about the thread mode stored in the mode register and
control the functional unit to process the plurality of threads,
wherein the plurality of thread modes includes a mode of allocating different sizes of threads less than a data size of the functional unit to the functional unit.
2. The multi-thread processor of claim 1 , wherein the plurality of thread modes includes a mode of allocating the plurality of threads to the functional unit, in which n is a natural number,
wherein the plurality of threads are a combination of threads of a size of 1/(2n) of a maximum processing capacity of the functional unit.
3. The multi-thread processor of claim 2 , wherein the size of one of the plurality of threads is a size obtained by dividing the maximum processing capacity by 2n and is greater than a scalar datapath size.
4. The multi-thread processor of claim 3 , wherein the controller is further configured to fetch as many instructions as the number of the plurality of threads, and process the plurality of threads allocated to the functional unit based on the fetched instruction.
5. The multi-thread processor of claim 2 , wherein the controller is further configured to generate an address to read data corresponding to the plurality of threads allocated to the functional unit, and
the multi-thread processor further includes a vector register transmitting read data to the functional unit based on the address generated in the controller.
6. A method of controlling a multi-thread processor, comprising:
storing information about thread mode corresponding to a task to be processed from among a plurality of thread modes, wherein the plurality of thread modes is divided based on a size and a number of a plurality of threads that is concurrently processed in a functional unit processing the plurality of threads; and
allocating the plurality of threads included in the task to the functional unit based on the information about the thread mode,
wherein the plurality of thread modes includes a mode of allocating different sizes of threads less than a data size of the functional unit to the functional unit.
7. The method of claim 6 , wherein the plurality of thread modes includes a mode of allocating at least one of the threads to the functional unit in which n is a natural number,
wherein the plurality of threads is a combination of threads of a size of 1/(2n) of a maximum processing capacity of the functional unit.
8. The method of claim 7 , wherein the size of one of the plurality of threads is a size obtained by dividing the maximum processing capacity by 2n and is greater than a scalar datapath size.
9. The method of claim 8 , further comprising:
fetching as many instructions as the number of the plurality of threads and processing the plurality of threads allocated to the functional unit based on the fetched instruction.
10. The method of claim 7 , further comprising:
generating an address to read data corresponding to the plurality of threads allocated to the functional unit; and
transmitting the read data to the functional unit based on the generated address.