Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; forming a first gate structure and a second gate structure on the first fin-shaped structure; using a patterned mask to remove the first gate structure and part of the first fin-shaped structure to form a first trench; and forming a first dielectric layer in the first trench to form a first single diffusion break (SDB) structure and around the second gate structure.
1. A semiconductor device, comprising:
a substrate having a first region and a second region;
a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein the first fin-shaped structure and the second fin-shaped structure are disposed extending along a first direction;
a first single diffusion break (SDB) structure extending along a second direction on the first region to separate the first fin-shaped structure into a first portion and a second portion; and
a second SDB structure extending along the second direction on the second region to separate the second fin-shaped structure into a third portion and a fourth portion, wherein a top surface of the first SDB structure is higher than a top surface of the first fin-shaped structure while a top surface of the second SDB structure is even with a top surface of the second fin-shaped structure.
2. The semiconductor device of claim 1 , wherein the first direction is orthogonal to the second direction.
3. The semiconductor device of claim 1 , wherein the first SDB structure and the second SDB structure comprise different materials.
4. The semiconductor device of claim 1 , further comprising:
a first gate structure on the first fin-shaped structure on the first region;
a second gate structure on the second fin-shaped structure on the second region;
a third gate structure on the second SDB structure on the second region; and
an interlayer dielectric (ILD) layer around the first gate structure, the second gate structure, and the third gate structure.
5. The semiconductor device of claim 4 , wherein top surfaces of the ILD layer, the first gate structure, the second gate structure, and the third gate structure are coplanar.
6. The semiconductor device of claim 4 , wherein a top surface of the first SDB structure is even with a top surface of the ILD layer.
7. The semiconductor device of claim 4 , wherein a top surface of the first SDB structure is even with top surfaces of the first gate structure, the second gate structure, and the third gate structure.
8. The semiconductor device of claim 1 , wherein a top surface of the second SDB structure is even with a top surface of the second fin-shaped structure.