IP Library › Granted Patent US 10,566,459
Granted Patent B2
US 10,566,459 · App. 15/795,736 · Granted Feb 18, 2020

Semiconductor device having a first region comprising silicon, oxygen and at least one metal element formed between an oxide semiconductor layer and an insulating layer

Inventors: Shunpei Yamazaki (Setagaya, JP); Akiharu Miyanaga (Hadano, JP); Masahiro Takahashi (Atsugi, JP); Hideyuki Kishida (Atsugi, JP); Junichiro Sakata (Atsugi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/7869H01L27/1225H01L29/42364H01L29/42384H01L29/518H01L29/66969H01L29/78606H01L29/78696
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Quick Facts
Patent No.
US 10,566,459
App. No.
15/795,736
Granted
Feb 18, 2020
Kind
B2
Abstract

An object is to provide a semiconductor device including an oxide semiconductor with stable electric characteristics can be provided. An insulating layer having many defects typified by dangling bonds is formed over an oxide semiconductor layer with an oxygen-excess mixed region or an oxygen-excess oxide insulating layer interposed therebetween, whereby impurities in the oxide semiconductor layer, such as hydrogen or moisture (a hydrogen atom or a compound including a hydrogen atom such as H 2 O), are moved through the oxygen-excess mixed region or oxygen-excess oxide insulating layer and diffused into the insulating layer. Thus, the impurity concentration of the oxide semiconductor layer is reduced.

Claims (37)

1. A semiconductor device comprising:

a gate electrode layer over a substrate;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer;

a source electrode layer and a drain electrode layer, each of the source electrode layer and the drain electrode layer being in contact with the oxide semiconductor layer;

a first insulating layer over the source electrode layer and the drain electrode layer, the first insulating layer comprising oxygen and silicon;

a first region between the oxide semiconductor layer and the first insulating layer; and

a second insulating layer covering the first insulating layer,

wherein the first region comprises oxygen, silicon and at least one of metal elements included in the oxide semiconductor layer,

wherein the gate insulating layer comprises a first layer and a second layer over the first layer,

wherein the first layer is a nitride layer and the second layer is an oxide layer,

wherein the first insulating layer is in contact with a top surface of the second layer of the gate insulating layer, and

wherein the second insulating layer is a nitride layer and in contact with a top surface of the first layer of the gate insulating layer.

2. A semiconductor device according to claim 1 , wherein the first region is in oxygen-excess state.

3. A semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises indium, gallium and zinc.

4. The semiconductor device according to claim 1 ,

wherein the first insulating layer has defects, and

wherein the first insulating layer is configured to bind and stabilize an impurity diffused from the oxide semiconductor layer.

5. A semiconductor device according to claim 1 , wherein a thickness of the first region is 0.1 nm to 30 nm.

6. A semiconductor device comprising:

a gate electrode layer over a substrate;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer;

a source electrode layer and a drain electrode layer, each of the source electrode layer and the drain electrode layer being in contact with the oxide semiconductor layer;

a first insulating layer over the source electrode layer and the drain electrode layer, the first insulating layer comprising oxygen and silicon;

a first region between the oxide semiconductor layer and the first insulating layer; and

a second insulating layer covering the first insulating layer,

wherein the oxide semiconductor layer comprises indium, gallium and zinc,

wherein the first region comprises indium, gallium, zinc, and silicon,

wherein the gate insulating layer comprises a first layer and a second layer over the first layer,

wherein the first insulating layer is in contact with a top surface of the second layer of the gate insulating layer, and

wherein the second insulating layer is a nitride layer and in contact with a top surface of the first layer of the gate insulating layer.

7. A semiconductor device according to claim 6 , wherein the first region is in oxygen-excess state.

8. The semiconductor device according to claim 6 ,

wherein the first insulating layer has defects, and

wherein the first insulating layer is configured to bind and stabilize an impurity diffused from the oxide semiconductor layer.

9. A semiconductor device according to claim 6 , wherein a thickness of the first region is 0.1 nm to 30 nm.

Priority Claims (1)
JP 2009-249876 · Oct 30, 2009 · national
Continuity (3)
Continuation 14474609 · Sep 2, 2014
Division 12912196 · Oct 26, 2010
Related Publication 20180053857A1 · Feb 22, 2018