Method and apparatus for accurate and efficient spectrum estimation using improved sliding DFT
An improved sliding discrete Fourier transform (SDFT) algorithm called CIC-SDFT and its apparatus are provided. An input signal is multiplied by a modulated twiddle factor, and is then processed by a modified cascade integrator-comb (CIC) filter. The CIC-SDFT comprises an integrator section and a comb section, with a downsampler disposed between the two sections to enable downsampling of the SDFT computations. Through addition of more integrator stages and comb stages to the CIC-SDFT, the accuracy of spectrum estimation may be improved in a computationally inexpensive manner and with less complexity than applying windowing functions to known SDFTs. Various embodiments provide a partially-nonrecursive method of CIC-SDFT that further decreases computational complexity.
1. An apparatus for spectrum estimation, comprising:
a signal processing circuit comprising:
a multiplier having a signal input, a coefficient input, and an output; and
a cascaded integrator-comb sliding discrete Fourier transform (CIC-SDFT) filter circuit disposed at the output of the multiplier, the CIC-SDFT filter circuit comprising:
one or more nonrecursive stages in series, and disposed at an input to the CIC-SDFT filter circuit; and
one or more recursive stages in series comprising a cascade of moving-average filters, and disposed at an output of a final nonrecursive stage of the one or more nonrecursive stages.
2. The apparatus of claim 1 , the CIC-SDFT filter circuit comprising:
an integrator section comprising one or more integrator stages in series, and disposed at an input to the CIC-SDFT filter circuit;
a downsampler disposed at an output of the integrator section and configured to generate a downsampled output signal; and
a comb section comprising one or more comb stages in series, and disposed at an output of the downsampler.
3. The apparatus of claim 2 , wherein a downsampling rate of the downsampler is permanent.
4. The apparatus of claim 2 , wherein a downsampling rate of the downsampler may be set by a user.
5. The apparatus of claim 2 , the integrator stages configured to add a previous output value to a modified output of the multiplier.
6. The apparatus of claim 2 , the comb stages configured to subtract a time delayed sample value from the downsampled output signal.
7. The apparatus of claim 1 each of the one or more nonrecursive stages configured to calculate (1+z −1 ) L , where L is a CIC filter order to be computed by the signal processing circuit.
8. The apparatus of claim 1 , each of the one or more nonrecursive stages comprising a downsampler.
9. The apparatus of claim 8 , the downsampler configured to downsample the modified input signal processed by the nonrecursive stage by 2.
10. The apparatus of claim 1 , wherein a number of nonrecursive stages is equal to log 2 of downsampling rate R and a number of recursive stages equal to filter order L.
11. The apparatus of claim 1 , wherein the signal processing circuit comprises a digital signal processing circuit.
12. The apparatus of claim 11 , wherein the digital signal processing circuit comprises at least one of a digital signal processor, an ASIC and a FPGA.
13. A method for improved spectrum estimation, comprising:
a signal processing circuit receiving an input signal;
the signal processing circuit multiplying the input signal by a modulated twiddle factor to create a modified input signal;
the signal processing circuit processing the modified input signal through one or more nonrecursive stages; and
the signal processing circuit processing an output of a last of the one or more nonrecursive stages through one or more recursive stages, which comprise a cascade of moving-average filters.
14. The method of claim 13 , each of the one or more nonrecursive stages configured to calculate (1+z −1 ) L , where L is a CIC filter order to be computed by the digital signal processing circuit.
15. The method of claim 13 , each of the one or more nonrecursive stages comprising a downsampler.
16. The method of claim 13 , wherein the signal processing circuit comprises at least one of a digital signal processor, an ASIC and a FPGA.