Gate driving circuit and display device including the same
A gate driving circuit includes: a plurality of stages, a k-th stage from among the plurality of stages, the k-th stage including: an input circuit to receive a previous carry signal and to pre-charge a first node; a first output circuit to output a k-th gate signal; a second output circuit to output a k-th carry signal; a discharge hold circuit to transmit a clock signal to a second node, and to discharge the second node with a second low voltage; a first pull down circuit to discharge the k-th gate signal with a first low voltage, and to discharge the first node and the k-th carry signal with the second low voltage; and a discharge circuit for discharging the k-th carry signal with the second low voltage in response to the previous carry signal.
1. A gate driving circuit comprising a plurality of stages,
a k-th stage from among the plurality of stages, where k is a natural number greater than or equal to 2, the k-th stage comprising:
an input circuit configured to receive a previous carry signal from a previous stage, and to pre-charge a first node;
a first output circuit configured to output a clock signal as a k-th gate signal in response to a signal of the first node;
a second output circuit configured to output the clock signal as a k-th carry signal in response to the signal of the first node;
a discharge hold circuit configured to transmit the clock signal to a second node in response to the clock signal, and to discharge the second node with a second low voltage in response to the k-th carry signal;
a first pull down circuit configured to discharge the k-th gate signal with a first low voltage in response to a signal of the second node and a next carry signal from a next stage, and to discharge the first node and the k-th carry signal with the second low voltage; and
a carry feedback circuit configured to feed back the k-th carry signal as the previous carry signal in response to a signal of the first node.
2. The gate driving circuit of claim 1 , further comprising:
a first input terminal configured to receive the previous carry signal;
a second input terminal configured to receive the next carry signal;
a carry output terminal configured to output the k-th carry signal; and
a third input terminal configured to receive the k-th carry signal outputted from the carry output terminal.
3. The gate driving circuit of claim 2 , wherein the carry feedback circuit comprises:
a first feedback transistor comprising a first electrode connected to the third input terminal, a second electrode, and a gate electrode connected to the third input terminal; and
a second feedback transistor comprising a first electrode connected to the second electrode of the first feedback transistor, a second electrode connected to the first input terminal, and a gate electrode connected to the first node.
4. The gate driving circuit of claim 2 , further comprising a discharge circuit configured to discharge the k-th carry signal with the second low voltage in response to the previous carry signal.
5. The gate driving circuit of claim 4 , wherein the discharge circuit comprises a first electrode connected to the carry output terminal, a second electrode connected to a second voltage terminal for receiving the second low voltage, and a gate electrode connected to the first input terminal.
6. The gate driving circuit of claim 5 , wherein the discharge circuit further comprises a second discharge transistor comprising a first electrode connected to the second node, a second electrode connected to the second voltage terminal, and a gate electrode connected to the first input terminal.
7. A display device comprising:
a display panel comprising a plurality of pixels respectively connected to a plurality of gate lines and a plurality of data lines;
a gate driving circuit comprising a plurality of stages for outputting gate signals to the plurality of gate lines; and
a data driving circuit configured to drive the plurality of data lines,
wherein a k-th stage from among the plurality of stages, where k is a natural number greater than or equal to 2, comprises:
an input circuit configured to receive a previous carry signal from a previous stage, and to pre-charge a first node;
a first output circuit configured to output a clock signal as a k-th gate signal in response to a signal of the first node;
a second output circuit configured to output the clock signal as a k-th carry signal in response to the signal of the first node;
a discharge hold circuit configured to transmit the clock signal to a second node in response to the clock signal, and to discharge the second node with a second low voltage in response to the k-th carry signal;
a first pull down circuit configured to discharge the k-th gate signal with a first low voltage in response to a signal of the second node and a next carry signal from a next stage, and to discharge the first node and the k-th carry signal with the second low voltage; and
a carry feedback circuit configured to feed back the k-th carry signal as the previous carry signal in response to the signal of the first node.