Memory device and operating method thereof

1. A memory system comprising:

a memory device configured to generate first read voltages and second read voltages, based on initial read voltages and first and second offset voltages, in response to a user read command, and output first data and second data, which are acquired by read operations on multi-bit memory cells, based on the first read voltages and the second read voltages; and

a memory controller configured to output the user read command,

wherein the memory controller includes a state counter configured to count numbers of data bits respectively corresponding to a plurality of threshold voltage states from the first data and the second data, and extract numbers of memory cells respectively included in a plurality of threshold voltage regions divided by the first read voltages and the second read voltages by calculating the counted result,

wherein the plurality of threshold voltage states includes a first threshold voltage state and a second threshold voltage state,

wherein the state counter extracts a number of memory cells included in a first region among the plurality of threshold voltage regions, based on a difference between a number of data bits corresponding to the first threshold voltage state, which is counted from the first data, and a number of data bits corresponding to the first threshold voltage state, which is counted from the second data, and

wherein the state counter extracts a first addition result by adding a number of data bits corresponding to the first threshold voltage state and a number of data bits corresponding to the second threshold voltage state, which are counted from the first data, extracts a second addition result by adding a number of data bits corresponding to the first threshold voltage state and a number of data bits corresponding to the second threshold voltage state, which are counted from the second data, and extracts a number of memory cells included in a second region among the plurality of threshold voltage regions, based on a difference between the first addition result and the second addition result.

2. The memory system of claim 1 , wherein a threshold voltage of the second region is larger than that of the first region.

3. The memory system of claim 1 , wherein the read operations include a two-time most significant bit (MSB) read operation and a two-time least significant bit (LSB) read operation.

4. The memory system of claim 1 ,

wherein the read operations include MSB read operations and LSB read operations, and

wherein the first data is generated through one of the MSB read operations and one of the LSB read operations, which are performed based on the first read voltages.

5. The memory system of claim 4 , wherein the MSB read operation is performed using two different voltages among the first read voltages, and one bit is generated from each of the multi-bit memory cells.

6. The memory system of claim 1 ,

wherein the memory device receives a read address from the memory controller,

wherein the user read command includes a preamble and a postamble, and

wherein the read address is input between the preamble and the postamble.

7. The memory system of claim 1 , wherein the memory device receives a first offset voltage and a second offset voltage from the memory controller.

8. The memory system of claim 7 , wherein the memory device receives the user read command after the first offset voltage is input.

9. The memory system of claim 1 , wherein the first read voltages have voltage levels lower by the first offset voltage than those of the respective initial read voltages.

10. A memory system comprising:

a memory device; and

a memory controller,

wherein the memory device includes:

multi-bit memory cells;

an input/output circuit configured to receive a user read command from the memory controller;

a voltage generating circuit configured to generate first read voltages, based on initial read voltages and a first offset voltage, and generate second read voltages, based on the initial read voltages and a second offset voltage, in response to the user read command; and

a page buffer group configured to store first data acquired by a first MSB read operation and a first LSB read operation on the multi-bit memory cells, based on the first read voltages, and store second data acquired by a second MSB read operation and a second LSB read operation on the multi-bit memory cells, based on the second read voltages,

wherein the memory controller includes a state counter configured to derive a first addition result by adding number of data bits respectively corresponding to a plurality of threshold voltage states from the first data, derive a second addition result by adding number of data bits respectively corresponding to a plurality of threshold voltage states from the second data, and extract a number of memory cells included in any one of a plurality of threshold voltage regions divided by the first read voltages and the second read voltages, based on a result obtained by subtracting the second addition result from the first addition result.

11. The memory system of claim 10 , wherein the first MSB read operation is performed using two different voltages among the first read voltages, and one bit is generated from each of the multi-bit memory cells.

12. The memory system of claim 10 ,

wherein the input/output circuit receives a read address from the memory controller,

wherein the user read command includes a preamble and a postamble, and

wherein the input/output circuit receives the read address between the preamble and the postamble.

13. A method for operating a memory system, the method comprising:

receiving a first user read command;

reading first data through read operations on a plurality of memory cells, using first read voltages, in response to the user read command;

receiving a second user read command and a first offset voltage;

reading second data through the read operations on the plurality of memory cells, using second read voltages generated based on the first read voltages and the first offset voltage, in response to the second user read command; and

extracting a number of memory cells included in a first region among a plurality of threshold voltage regions divided by the first read voltages and the second read voltages by subtracting a number of data bits corresponding a first threshold voltage state, which is extracted from the second data, from a number of data bits corresponding to the first threshold voltage state, which is extracted from the first data.

14. The method of claim 13 , further comprising:

deriving a first addition result by adding a number of data bits corresponding to the first threshold voltage state and a number of data bits corresponding to a second threshold voltage state, which are extracted from the first data;

deriving a second addition result by adding a number of data bits corresponding to the first threshold voltage state and a number of data bits corresponding to the second threshold voltage state, which are extracted from the second data; and

extracting a number of memory cells included in a second region among the plurality of threshold voltage regions by subtracting the second addition result from the first addition result.

15. The method of claim 14 , wherein a threshold voltage of the second region is larger than that of the first region.

16. The method of claim 15 , wherein the read operation is performed using two different voltages among the first read voltages or the second read voltages, and one bit is extracted from each of the memory cells.

17. The method of claim 14 ,

further comprising receiving a read address,

wherein the user read command includes a preamble and a postamble, and

wherein the read address is input between the preamble and the postamble.

18. The method of claim 15 , wherein the receiving of the user read command includes:

receiving the user read command for an MSB read operation; and

receiving the user read command for an LSB read operation.