IP Library › Granted Patent US 10,573,740
Granted Patent B2
US 10,573,740 · App. 16/457,807 · Granted Feb 25, 2020

Method of producing semiconductor device

Inventor: Tsutomu Kiyosawa (Toyama, JP)
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
H01L29/7805H01L29/0696H01L29/086H01L29/1045H01L29/1095H01L29/1608H01L29/41741H01L29/41766H01L29/42368H01L29/66068H01L29/7801H01L29/7802H01L29/7827H01L29/7828H01L2924/13091
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,573,740
App. No.
16/457,807
Granted
Feb 25, 2020
Kind
B2
Abstract

A method of producing a semiconductor device includes the following steps (A), (B), and (C). In the step (A), a semiconductor epitaxial wafer is prepared. The semiconductor epitaxial wafer includes a body region. In the step (B), a channel layer is formed by epitaxial growth. In the step (C), a gate insulation film is formed on the channel layer. The channel layer contains impurity at a concentration ranging from 1×10 18 cm −3 to 1×10 19 cm −3 , inclusive, and has a thickness ranging from 10 nm to 100 nm, inclusive. In the steps of (B) and (C), a condition for the epitaxial growth and a condition for forming the gate insulation film are controlled so that a thickness distribution in the channel layer and a thickness distribution in the gate insulation film are positively correlated to each other.

Claims (7)

1. A method of producing a semiconductor device, the method comprising steps of:

(A) preparing a semiconductor epitaxial wafer which includes a semiconductor wafer, and a semiconductor layer disposed on a main surface of the semiconductor wafer, the semiconductor layer containing a first conductivity type impurity, the semiconductor epitaxial wafer including a plurality of device regions, each of which includes a body region of a second conductivity type in contact with the semiconductor layer, and a source region of the first conductivity type in contact with the body region;

(B) forming a channel layer which is in contact with at least a part of the body region by epitaxial growth of a semiconductor on a surface of the semiconductor layer; and

(C) forming a gate insulation film on the channel layer, wherein:

the channel layer contains the first conductivity type impurity at a concentration ranging from 1×10 18 cm −3 to 1×10 19 cm −3 , inclusive, and has a thickness ranging from 10 nm to 100 nm, inclusive, and

in the steps of (B) and (C), a condition for the epitaxial growth and a condition for forming the gate insulation film are controlled so that, in a plane parallel to the main surface of the semiconductor wafer, a thickness distribution in the channel layer and a thickness distribution in the gate insulation film are positively correlated to each other.

2. The method according to claim 1 , wherein the semiconductor wafer is a silicon carbide wafer, the semiconductor layer is a silicon carbide semiconductor layer, and the channel layer is constituted by a silicon carbide semiconductor.

Priority Claims (1)
JP 2017-041696 · Mar 6, 2017 · national
Continuity (3)
Division 16184734 · Nov 8, 2018
Division 15896490 · Feb 14, 2018
Related Publication 20190326428A1 · Oct 24, 2019
Cited By (1)
US 12,376,331