Apparatus and method for generating stable reference current
An apparatus is provided which comprises: an oscillator to generate a first clock having a first frequency; a divider coupled to the oscillator, wherein the divider is to generate a second clock having a second frequency; and a current reference generator comprising a switched capacitor circuitry which is to receive the second clock directly or indirectly.
1. An apparatus comprising:
an oscillator to generate a first clock having a first frequency;
an amplifier coupled to an output of the oscillator, wherein the amplifier is to amplify the first clock to generate an amplified first clock;
a first divider coupled to the output of the amplifier, wherein the first divider is to divide the amplified first clock and is to generate a second clock having a second frequency;
a second divider coupled to the output of the amplifier, wherein the second divider is to divide the amplified first clock to generate a third clock having a third frequency;
a selection circuitry to select one of the second clock or a reference clock as an output clock;
a current reference generator comprising a switched capacitor circuitry, wherein the switched capacitor circuitry is to apply the output clock via the selection circuitry, and wherein the current reference generator is to generate a reference current in accordance with an output of the switched capacitor circuitry.
2. The apparatus of claim 1 , wherein the current reference generator comprises:
a sequential logic to receive the second clock, and to generate sampled control signals for at least two transistors of the switched capacitor circuitry.
3. The apparatus of claim 1 , wherein the current reference generator comprises an amplifier having a first input to receive a reference voltage and a second input coupled to the switched capacitor circuitry.
4. The apparatus of claim 3 , wherein the current reference generator comprises a transistor, which is to be controlled by an output of the amplifier.
5. The apparatus of claim 1 , wherein the divider is one of an integer divider or fractional divider.
6. The apparatus of claim 1 comprises a charge pump to receive the reference current from the current reference generator.
7. The apparatus of claim 6 comprises a loop filter coupled to the charge pump and the oscillator.
8. The apparatus of claim 1 , wherein the first divider is an adaptive divider such that the second frequency can be adjusted in response to a control.
9. The apparatus of claim 1 , wherein the oscillator is one of: a voltage control oscillator (VCO), an Inductor-Capacitor (LC) based VCO, or a digitally controlled oscillator (DCO).
10. A system comprising:
a memory;
a processor coupled to the memory, the processor having a phase locked loop (PLL) circuitry which includes:
an oscillator to generate a first clock having a first frequency;
an amplifier coupled to an output of the oscillator, wherein the amplifier is to amplify the first clock to generate an amplified first clock;
a first divider coupled to the output of the amplifier, wherein the first divider is to divide the amplified first clock and is to generate a second clock having a second frequency;
a second divider coupled to the output of the amplifier, wherein the second divider is to divide the amplified first clock to generate a third clock having a third frequency;
a selection circuitry to select one of the second clock or a reference clock as an output clock; and
a current reference generator comprising a switched capacitor circuitry, wherein the switched capacitor circuitry is to apply the output clock via the selection circuitry, and wherein the current reference generator is to generate a reference current in accordance with an output of the switched capacitor circuitry; and
a wireless interface to allow the processor to communicate with another device.
11. The system of claim 10 , wherein the PLL is a charge-pump based PLL.
12. The system of claim 10 , wherein the PLL comprises a charge pump which is to receive the reference current from the current reference generator.
13. The system of claim 10 comprises a display which is communicatively coupled to the processor.
14. The system of claim 10 , wherein the first divider is an adaptive divider such that the second frequency can be adjusted in response to a control.
15. The system of claim 10 , wherein the oscillator is one of: a voltage control oscillator (VCO), an Inductor-Capacitor (LC) based VCO, or a digitally controlled oscillator (DCO).
16. An apparatus comprising:
an oscillator to generate a first clock having a first frequency;
an amplifier coupled to an output of the oscillator, wherein the amplifier is to amplify the first clock and is to generate a second clock with the first frequency;
a first divider coupled to an output of the amplifier, wherein the first divider is to divide the second clock and to generate a third clock of a second frequency, wherein the third clock is eventually received as input by a phase detector;
a second divider coupled to the output of the amplifier and a multiplexer, wherein the second divider is to divide the second clock and is to generate a fourth clock with a third frequency; and
a current reference generator comprising a switched capacitor circuitry, wherein the switched capacitor circuitry is to apply the fourth clock via the multiplexer, and wherein the current reference generator is to generate a reference current in accordance with an output of the switched capacitor circuitry.
17. The apparatus of claim 16 , wherein the multiplexer is to receive a reference clock, which is also received by the phase detector.
18. The apparatus of claim 16 , wherein an output of the multiplexer is a clock, which is one of the reference clock or the fourth clock, wherein the output of the multiplexer is coupled to a clock input of a sequential logic, and wherein an output of the sequential logic is coupled to the switched capacitor circuitry.
19. The apparatus of claim 16 , wherein the switched capacitor circuitry is coupled to an input of an amplifier.