Tamper-respondent assembly with interconnect characteristic(s) obscuring circuit layout
Tamper-respondent assemblies and methods of fabrication are provided which include at least one tamper-respondent sensor and a detector. The at least one tamper-respondent sensor includes conductive lines which form, at least in part, at least one tamper-detect network of the tamper-respondent sensor(s). In addition, the tamper-respondent sensor(s) includes at least one interconnect element associated with one or more conductive lines of the conductive lines forming, at least in part, the tamper-detect network(s). The interconnect element(s) includes at least one interconnect characteristic selected to facilitate obscuring a circuit lay of the at least one tamper-detect network. In operation, the detector monitors the tamper-detect network(s) of the tamper-respondent sensor(s) for a tamper event.
1. A fabrication method comprising:
fabricating a tamper-respondent assembly, the fabricating comprising:
providing at least one tamper-respondent sensor including:
conductive lines forming, at least in part, at least one tamper-detect network of the at least one tamper-respondent sensor; and
at least one interconnect element associated with one or more conductive lines of the conductive lines forming, at least in part, the at least one tamper-detect network, the at least one interconnect element comprising at least one interconnect characteristic selected to facilitate obscuring a circuit layout of the at least one tamper-detect network;
providing a detector to monitor the at least one tamper-detect network of the at least one tamper-respondent sensor for a tamper event; and
wherein:
the at least one tamper-respondent sensor comprises at least one layer, and different conductive lines of the conductive lines are disposed on different surfaces of the at least one layer, and the at least one interconnect element comprises multiple interconnect vias between the different conductive lines disposed on the different surfaces;
an interconnect via of the multiple interconnect vias is undetectable via x-ray analysis;
an other interconnect via of the multiple interconnect vias comprises a fictitious interconnect via not electrically connecting two or more different conductive lines;
the interconnect via and the other interconnect via are formed of different interconnect materials; and
the other interconnect via is detectable by x-ray, appearing in x-ray analysis to be an actual electrical interconnect via.
2. The method of claim 1 , wherein the conductive lines are formed of a conductive material, the conductive material and the interconnect material being different materials.
3. The method of claim 2 , wherein the conductive material is detectable by x-ray.
4. The method of claim 1 , wherein the interconnect via comprises an electrical interconnect material on a wall of the interconnect via with a thickness making the interconnect via difficult to detect by x-ray.
5. The method of claim 4 , wherein the electrical interconnect material is selected from a group consisting of an electroless seed layer, a graphite seed layer or a sputtered interconnect material.