Memory system
A memory system includes a memory controller and a memory. The memory controller selectively operates in a first mode and a second mode. In the first mode, the memory controller transmits a first command continuously during a plurality of clock cycles. In the second mode, the memory controller to mix a second command with the first command and transmit the mixture of the first command and the second command. The memory changes command latch timing depending on the first or second mode.
1. A synchronous dynamic random access memory (SDRAM) device comprising:
a memory cell array; and
a control logic to
sequentially receive an active command during 2*N clock cycles and receive a column address strobe (CAS) command during N clock cycles in a first mode, the N being an integer and 2*N clock cycles indicating doubled N clock cycles; and
receive an active-CAS command corresponding to a combination of the active command and the CAS command during 2*N clock cycles in a second mode, wherein the active-CAS command is one of an active-read command corresponding to a combination of the active command and a read command and an active-write command corresponding to a combination of the active command and a write command.
2. The SDRAM device of claim 1 , wherein a CAS command to CAS command delay (tCCD) is 3*N clock cycles in the first mode and the tCCD is 2*N clock cycles in the second mode respectively, the tCCD is a minimally required delay between two successive CAS commands.
3. The SDRAM device of claim 1 , wherein the CAS command is one of a read command and a write command.
4. The SDRAM device of claim 1 , wherein the N is two.
5. The SDRAM device of claim 1 , wherein:
the active command includes a row address; and
the CAS command includes a column address.
6. The SDRAM device of claim 1 , wherein the active-CAS command includes a row address and a column address.
7. The SDRAM device of claim 1 , wherein the memory cell array includes a plurality of memory layers which are stacked vertically and the memory layers are electrically connected by through silicon vias (TSVs).
8. A memory controller controlling a synchronous memory device, the memory controller to:
sequentially transmit an active command during 2*N clock cycles and transmit a column address strobe (CAS) command during N clock cycles in a first mode, the N being an integer and 2*N clock cycles indicating doubled N clock cycles; and
transmit an active-CAS command corresponding to a combination of the active command and the CAS command during 2*N clock cycles in a second mode, wherein the active-CAS command includes a row address and a column address.
9. The memory controller of claim 8 , wherein a CAS command to CAS command delay (tCCD) is 3*N clock cycles in the first mode and the tCCD is 2*N clock cycles in the second mode respectively, the tCCD is a minimally required delay between two successive CAS commands.
10. The memory controller of claim 8 , wherein the CAS command is one of a read command and a write command.
11. The memory controller of claim 8 , wherein the active-CAS command is one of an active-read command corresponding to a combination of the active command and a read command and an active-write command corresponding to a combination of the active command and a write command.
12. The memory controller of claim 8 , wherein the N is two.
13. The memory controller of claim 8 , wherein:
the active command includes a row address; and
the CAS command includes a column address.
14. An apparatus, comprising:
an interface coupled to a memory; and
a memory controller to selectively operate in a first mode and a second mode, the memory controller to transmit a first command continuously through the interface during a first plurality of clock cycles and a second command continuously through the interface during a second plurality of clock cycles in the first mode and to combine a second command with the first command and transmit a third command corresponding to the combination of the first command and the second command through the interface during a third plurality of clock cycles in the second mode.
15. The apparatus of claim 14 , wherein:
the first command includes a row address;
the second command includes a column address; and
the third command includes both of the row address and the column address.
16. The apparatus of claim 14 , wherein a number of the first plurality of clock cycles is less than a number of a sum of the second plurality of clock cycles and the third plurality of clock cycles.
17. The apparatus of claim 14 , wherein:
the first command is an active command including a row address, and
the second command is a column address strobe (CAS) command including a column address.
18. The apparatus of claim 17 , wherein the memory controller is to:
transmit the active command during 4 clock cycles and transmit the CAS command during 2 clock cycles after transmitting the active command in the first mode; and
transmit the third command during 4 clock cycles in the second mode.