Method and apparatus for using an error signal to indicate a write request error and write request acceptance

1. An apparatus in communication with a host memory controller over a bus, comprising:

memory module controller for a memory module having memory chips to store data, to:

detect a write error in response to a write request, from the host memory controller, directed to the memory chips in the memory module; and

assert an error signal on the bus to the host memory controller in response to detecting the write error to cause the host memory controller to determine whether the error signal is received within a predetermined time after each of a plurality of write requests were sent and resend each of the plurality of write requests that were sent within the predetermined time of receiving the error signal, and wherein the host memory controller processes each of the plurality of write requests as having completed without error if the error signal is not detected within the predetermined time after sending the write request from the host memory controller.

2. The apparatus of claim 1 , wherein the error signal is an only communication to the host memory controller concerning the detected write error.

3. The apparatus of claim 1 , wherein the error signal is asserted on an error pin on the bus.

4. The apparatus of claim 1 , wherein the memory module controller is to indicate successful completion of each of the plurality of write requests by not sending the error signal within the predetermined time of each of the plurality of write requests.

5. An apparatus coupled to a memory module over a bus, wherein the memory module has memory chips to store data, comprising:

host memory controller to:

send a plurality of write requests to store data in at least one of the memory chips in the memory module;

detect an error signal asserted from the memory module after the sending of the plurality of write requests to the memory module;

determine whether each of the plurality of write requests were sent within a predetermined time of detecting the error signal, wherein the predetermined time is used for comparison to determine whether each of the plurality of write requests completed without error;

resend each of the plurality of write requests determined to have been sent within the predetermined time only when the error signal is received within the predetermined time after sending the write request; and

process each of the plurality of write requests as having completed successfully if the error signal is not received within the predetermined time after the sending of the write request to the memory module.

6. The apparatus of claim 5 , wherein the error signal comprises an error low signal asserted on an error pin on the bus.

7. The apparatus of claim 5 , wherein each of the plurality of write requests are resent if the error signal is sent for an error unrelated to a write request error when the error signal is received within the predetermined time.

8. The apparatus of claim 5 , wherein the host memory controller further:

performs an error handling operation unrelated to write request errors determined for the error signal.

9. The apparatus of claim 8 , wherein the error handling operation unrelated to write errors is performed in addition to resending the write requests.

10. A method comprising:

detecting a write error in response to a write request directed to memory chips in a memory module; and

asserting an error signal on a bus to a host memory controller in response to detecting the write error to cause the host memory controller to determine whether the error signal is received within a predetermined time after each of a plurality of write requests were sent and resend each of the plurality of write requests that were sent within the predetermined time of receiving the error signal, and wherein the host memory controller processes each of the plurality of write requests as having completed without error if the error signal is not detected within the predetermined time after sending the write request from the host memory controller.

11. The method of claim 10 , wherein the error signal is an only communication to the host memory controller concerning the detected write error.

12. The method of claim 10 , wherein the error signal is asserted on an error pin on the bus.

13. The method of claim 10 , further comprising:

indicating successful completion of each of the plurality of write requests by not sending the error signal within the predetermined time of each of the plurality of write requests.

14. A method, comprising:

sending a plurality of write requests to at least one memory chip in a memory module over a bus;

detecting an error signal asserted from the memory module after the sending of the write requests to the memory module;

determining whether each of the plurality of write requests were sent within a predetermined time of detecting the error signal, wherein the predetermined time is used for comparison to determine whether each of the plurality of write requests completed without error;

resending each of the plurality of write requests determined to have been sent within the predetermined time only when the error signal is received within the predetermined time after sending the write request; and

processing each of the plurality of write requests as having completed successfully if the error signal is not received within the predetermined time after the sending of the write request to the memory module.

15. The method of claim 14 , wherein the error signal comprises an error low signal asserted on an error pin on the bus.

16. The method of claim 14 , wherein each of the plurality of write requests are resent if the error signal is sent for an error unrelated to a write request error when the error signal is received within the predetermined time.

17. The method of claim 14 , further comprising:

performing an error handling operation unrelated to write request errors determined for the error signal.

18. The method of claim 17 , wherein the error handling operation unrelated to write errors is performed in addition to resending the write requests.

19. The apparatus of claim 1 , wherein the error signal is an error low signal, and wherein the memory module controller is further to:

maintain an error high signal active on the bus to indicate no error has occurred until asserting the error signal.

20. The method of claim 10 , wherein the error signal is an error low signal, further comprising:

maintaining an error high signal active on the bus to indicate no error has occurred until asserting the error signal.