Controlling timing in computer processing

1. A computer program product having a non-transitory computer readable medium tangibly recording computer program logic for controlling switching circuitry, the computer program product comprising:

code to execute a switch control instruction which when executed causes a processing unit to control the switching circuitry to connect a set of connection wires of the processing unit to a switching fabric to receive a data packet at a predetermined received time, the switch control instruction comprising a delay control field which holds a value defining a delay between issuance of the instruction in a sequence of instructions and its execution by an execution unit.

2. A computer program product according to claim 1 , wherein the switch control instruction comprises a switch control field which selects one of multiple inputs of the switching circuitry connected to the corresponding connectors of the switching fabric on which the data packet is expected at the received time.

3. A computer program product according to claim 1 , wherein the value defining the delay causes the switch control instruction to be executed at least one execution cycle prior to the predetermined received time.

4. A computer program product according to claim 1 , wherein the value defines the delay in terms of execution cycles.

5. A computer program product according to claim 1 , wherein the switch control instruction further defines a send function which causes a data packet destined for a recipient processing unit to be transmitted on a set of connection wires connected to the processing unit, the data packet having no destination identifier but being transmitted at a predetermined transmit time, whereby the processing unit is configured to operate to transmit a data packet and to control its switching circuitry to receive a different data packet from another processing unit in a single execution cycle.

6. A computer program product according to claim 1 , wherein the switch control instruction further defines a memory pointer update function which updates a memory pointer identifying a memory location in a data storage for storing the data packet which is received at a recipient processing unit.

7. A method of computing a function in a computer comprising:

a plurality of processing units each having instruction storage holding a local program,

an execution unit for executing the local program, and a data storage for holding data,

an input interface with a set of input wires and an output interface with a set of output wires;

a switching fabric connected to each of the processing units by the respective sets of output wires and connectable to each of the processing units by their respective input wires by switching circuitry controllable by each processing unit, the method comprising:

the processing units executing their local programs according to a common clock,

wherein at a predetermined switch time one of the processing units executes a switch control instruction from its local program to control the switching circuitry to connect its input wires to the switching fabric to receive a data packet at a received time,

wherein the predetermined switch time is controlled by a delay control field in the switch control instruction, the delay control field holding a value defining a delay between issuance of the switch control instruction and its execution by the execution unit.

8. A method according to claim 7 , wherein the switch control instruction comprises a switch control field which selects one of multiple inputs of the switching circuitry connected to the corresponding connectors of the switching fabric on which the data packet is expected at the received time.

9. A method according to claim 7 , wherein the value defining the delay causes the switch control instruction to be executed at least one execution cycle prior to the predetermined received time.

10. A method according to claim 7 , wherein the value defines the delay in terms of execution cycles.

11. A method according to claim 7 , wherein the switch control instruction further defines a send function which causes a data packet destined for a recipient processing unit to be transmitted on a set of connection wires connected to the processing unit, the data packet having no destination identifier but being transmitted at a predetermined transmit time, whereby the processing unit is configured to operate to transmit a data packet and to control its switching circuitry to receive a different data packet from another processing unit in a single execution cycle.

12. A method according to claim 7 , wherein the switch control instruction further defines a memory pointer update function which updates a memory pointer identifying a memory location in the data storage for storing the data packet which is received at a recipient processing unit.

13. A computer comprising:

a plurality of processing units each having instruction storage holding a local program, an execution unit for executing the local program, a data storage for holding data, and an input interface with a set of input wires and an output interface with a set of output wires;

a switching fabric connected to each of the processing units by the respective sets of output wires and connectable to each of the processing units by their respective input wires by switching circuitry controllable by each processing unit, wherein the processing units are configured to execute their local programs according to a common clock,

wherein one of the plurality of processing units is configured to, at a predetermined switch time, execute a switch control instruction from its local program to control the switching circuitry to connect its input wires to the switching fabric to receive a data packet at a received time, wherein the predetermined switch time is controlled by a delay control field in the switch control instruction, the delay control field holding a value defining a delay between issuance of the switch control instruction and its execution by the execution unit.

14. A computer according to claim 13 , wherein the switch control instruction comprises a switch control field which selects one of multiple inputs of the switching circuitry connected to the corresponding connectors of the switching fabric on which the data packet is expected at the received time.

15. A computer according to claim 13 , wherein the value defining the delay causes the switch control instruction to be executed at least one execution cycle prior to the predetermined received time.

16. A computer according to claim 13 , wherein the value defines the delay in terms of execution cycles.

17. A computer according to claim 13 , wherein the switch control instruction further defines a send function which causes a data packet destined for a recipient processing unit to be transmitted on a set of connection wires connected to the processing unit, the data packet having no destination identifier but being transmitted at a predetermined transmit time, whereby the processing unit is configured to operate to transmit a data packet and to control its switching circuitry to receive a different data packet from another processing unit in a single execution cycle.

18. A computer according to claim 13 , wherein the switch control instruction further defines a memory pointer update function which updates a memory pointer identifying a memory location in the data storage for storing the data packet which is received at a recipient processing unit.