Flipped vertical field-effect-transistor
Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an insulator layer on the substrate, a first doped layer on the insulator layer, at least one fin structure in contact with the doped layer, a dielectric layer surrounding a portion of the fin structure, a gate layer on the dielectric layer, a second doped layer in contact with the fin structure, a first contact area in contact with the second doped layer, and at least a first interconnect in contact with the first contact area. The structure is flipped bonded to a second substrate. The first substrate and the insulator layer are removed to expose the first doped layer. A second contact area is formed in contact with the first doped layer. At least a second interconnect is formed in contact with the second contact area.
1. A circuit comprising:
a top supply rail and a top ground rail disposed within a top level of the circuit;
a bottom supply rail and a bottom ground rail disposed within a bottom level of the circuit;
at least one input line disposed within a middle level of the circuit;
an output line disposed within the top level of the circuit;
at least one p-type vertical field-effect-transistor (FET) coupled to one of the bottom supply rail and the top supply rail; and
at least one n-type vertical FET coupled to one of the bottom ground rail and the top ground rail,
wherein, the at least one p-type vertical FET and the at least one n-type vertical FET each comprise a bottom source/drain layer disposed below a gate structure and a top source/drain layer disposed above the gate structure.
2. The circuit of claim 1 , wherein the at least one p-type vertical FET is coupled to the at least one input line, the output line, and the bottom supply rail.
3. The circuit of claim 1 , wherein the at least one p-type vertical FET comprises a plurality of p-type vertical FETs, wherein each p-type vertical FET of the plurality of p-type vertical FETs is coupled to the at least one input line, the output line, and the bottom supply rail.
4. The circuit of claim 1 , wherein the at least one n-type vertical FET is coupled to the at least one input line and, the output line, and the bottom ground rail.
5. The circuit of claim 1 , wherein the at least one n-type vertical FET comprises a plurality of n-type vertical FETs coupled to the at least one input line and having at least one n-type vertical FET coupled to the output line, where the plurality of n-type vertical FETs comprises an even number of plurality of n-type vertical FETs, and wherein at least one n-type vertical FET in the plurality of n-type vertical FETs is coupled to the top ground rail.
6. The circuit of claim 1 , wherein the at least one n-type vertical FET comprises a plurality of n-type vertical FETs coupled to the at least one input line and having at least one n-type vertical FET coupled to the output line, where the plurality of n-type vertical FETs comprises an odd number of plurality of n-type vertical FETs, and wherein at least one n-type vertical FET in the plurality of n-type vertical FETs is coupled to the bottom ground rail.
7. The circuit of claim 1 , wherein the at least one p-type vertical FET comprises a plurality of p-type vertical FETs coupled to the at least one input line and having at least one p-type vertical FET coupled to the output line, where the plurality of p-type vertical FETs comprises an even number of plurality of p-type vertical FETs, and wherein at least one p-type vertical FET in the plurality of p-type vertical FETs is coupled to the top supply rail.
8. The circuit of claim 1 , wherein the at least one p-type vertical FET comprises a plurality of p-type vertical FETs coupled to the at least one input line and having at least one p-type vertical FET coupled to the output line, where the plurality of p-type vertical FETs comprises an odd number of plurality of p-type vertical FETs, and wherein at least one p-type vertical FET in the plurality of p-type vertical FETs is coupled to the bottom supply rail.
9. A circuit comprising:
a top supply rail and a top ground rail disposed within a top level of the circuit;
a bottom supply rail and a bottom ground rail disposed within a bottom level of the circuit;
at least one input line disposed within a middle level of the circuit;
an output line disposed within the top level of the circuit;
at least one p-type vertical field-effect-transistor (FET) coupled to at least the output line and the bottom supply rail;
at least one n-type vertical FET coupled to at least the output line and the bottom ground rail.
10. The circuit of claim 9 , wherein a source terminal of the at least one p-type vertical FET and a source terminal of the at least one n-type vertical FET are coupled to the output line.
11. The circuit of claim 9 , wherein a drain terminal of the at least one p-type vertical FET is coupled to the output line.
12. The circuit of claim 9 , wherein a drain terminal of the at least one n-type vertical FET is coupled to the output line.
13. The circuit of claim 9 , wherein a source terminal of the at least one p-type vertical FET is coupled to the bottom supply rail, and a source terminal of the at least one n-type vertical FET is coupled to the bottom supply rail.
14. A circuit comprising:
a bottom supply rail and a bottom ground rail disposed within a bottom level of the circuit;
at least one input line disposed within a middle level of the circuit;
an output line disposed within a top level of the circuit;
a plurality of p-type vertical field-effect-transistors (FETs) coupled to the at least one input line and having at least one p-type vertical FET coupled to the output line, wherein at least one p-type vertical FET in the plurality of p-type vertical FETs is coupled to the bottom supply rail; and
at least one n-type vertical FET coupled to one of the bottom ground rail and a top ground rail.
15. The circuit of claim 14 , wherein the at least one n-type vertical FET is coupled to the at least one input line and, the output line, and the bottom ground rail.
16. The circuit of claim 14 , wherein the at least one n-type vertical FET comprises a plurality of n-type vertical FETs coupled to the at least one input line and having at least one n-type vertical FET coupled to the output line, where the plurality of n-type vertical FETs comprises an even number of plurality of n-type vertical FETs, and wherein at least one n-type vertical FET in the plurality of n-type vertical FETs is coupled to the top ground rail.
17. The circuit of claim 14 , wherein the at least one n-type vertical FET comprises a plurality of n-type vertical FETs coupled to the at least one input line and having at least one n-type vertical FET coupled to the output line, where the plurality of n-type vertical FETs comprises an odd number of plurality of n-type vertical FETs, and wherein at least one n-type vertical FET in the plurality of n-type vertical FETs is coupled to the bottom ground rail.
18. The circuit of claim 14 , wherein the plurality of p-type vertical FETs comprises an odd number of p-type vertical FETs.
19. The circuit of claim 14 , wherein a source terminal of the at least one p-type vertical FET is coupled to the bottom supply rail.
20. The circuit of claim 14 , wherein a source terminal of the least one n-type vertical FET is coupled to the bottom ground rail.