Stacked series connected VFETs for high voltage applications
A method of forming a semiconductor device and resulting structures having stacked vertical field effect transistors (VFETs) connected in series. A first semiconductor fin and a second semiconductor fin are formed on a doped region of a substrate. A shared gate is formed over a channel region of the first semiconductor fin and a channel region of the second semiconductor fin. A shared epitaxy region is formed on a surface of the first semiconductor fin and a surface of the second semiconductor fin.
1. A method for forming a semiconductor device, the method comprising:
forming a first vertical semiconductor fin and a second vertical semiconductor fin on a doped region of a substrate;
forming a shared gate over a channel region of the first vertical semiconductor fin and a channel region of the second vertical semiconductor fin;
forming a first upper surface of the first vertical semiconductor fin and a second surface of the second vertical semiconductor fin each above an upper surface of the shared gate; and
growing first and second epitaxy regions from the first and second upper surfaces and across the shared gate from the first upper surface to the second upper surface so as to form the air gap between the shared epitaxy region and a surface of the shared gate to form a floating shared epitaxy region on a top surface of the first vertical semiconductor fin and a top surface of the second vertical semiconductor fin such that the shared gate is below the shared epitaxy region and is interposed between the shared epitaxy region and the doped region of the substrate, the floating shared epitaxy region having an air gap between a lower epitaxy surface and the shared gate,
wherein the floating shared epitaxy region connects the first and second vertical semiconductor fins are in series and excludes a contact formed thereon so to define a channel that extends from the first vertical semiconductor fin through the floating shared epitaxy region and to the second vertical semiconductor fin.
2. The method of claim 1 , further comprising:
growing the first and the second epitaxy regions until the first epitaxy region merges with the second epitaxy region.
3. The method of claim 1 , wherein the doped region comprises a first portion and a second portion, the first semiconductor fin formed on the first portion and the second semiconductor fin formed on the second portion; further comprising forming a shallow trench isolation region in the substrate, the shallow trench isolation region between the first portion and the second portion of the doped region.
4. The method of claim 1 , further comprising:
forming a first contact in the first portion of the doped region; wherein the first contact is electrically coupled to a positive supply voltage;
forming a second contact in the second portion of the doped region without forming a contact in the shared epitaxy region such that a current flows between the first contact and the second contact thereby forming a serial connection between the first contact, first vertical semiconductor fin, the second vertical semiconductor fin, and the second contact.
5. The method of claim 4 , wherein the positive supply voltage is greater than about 1 volt.
6. A method for forming a semiconductor device, the method comprising:
forming a first vertical semiconductor fin on a first portion of a doped region of a substrate;
forming a second vertical semiconductor fin on a second portion of the doped region of the substrate;
forming a gate over a channel region of the first vertical semiconductor fin and a channel region of the second vertical semiconductor fin;
forming a first top surface of the first vertical semiconductor fin and a second top surface of the second vertical semiconductor fin each above an upper surface of the shared gate;
forming a first epitaxy region on the first top surface of the first vertical semiconductor fin;
forming a second epitaxy region on the second top surface of the second vertical semiconductor fin; and
growing the first and the second epitaxy regions across the shared gate until the first epitaxy region merges with the second epitaxy region to define a floating shared epitaxy region such that the gate is below the shared epitaxy region and is interposed between the shared epitaxy region and the doped region of the substrate, the floating shared epitaxy region having an air gap between a lower epitaxy surface and the gate,
wherein the floating shared epitaxy region connects the first and second vertical semiconductor fins in series such that an applied current flows serially from the first portion of the doped region through the channel region of the first vertical semiconductor fin, across the shared epitaxy region, and through the channel region of the second vertical semiconductor fin to the second portion of the doped region.
7. The method of claim 6 , further comprising forming a shallow trench isolation region in the substrate, the shallow trench isolation region between the first portion and the second portion of the doped region.
8. The method of claim 7 , further comprising:
forming a first contact in the first portion of the doped region; and
forming a second contact in the second portion of the doped region;
wherein the floating shared epitaxy region excludes a contact such that a current flows between the first contact and the second contact thereby forming a serial connection between the first contact, first vertical semiconductor fin, the second vertical semiconductor fin, and the second contact.
9. The method of claim 8 , wherein the second contact is electrically coupled to a positive supply voltage.
10. The method of claim 9 , wherein the positive supply voltage is greater than about 1 volt.
11. A method for forming a semiconductor device, the method comprising:
forming a first vertical semiconductor fin and a second vertical semiconductor fin on a doped region of a substrate;
forming a shared gate over a channel region of the first vertical semiconductor fin and a channel region of the second vertical semiconductor fin;
forming a first upper surface of the first vertical semiconductor fin and a second surface of the second vertical semiconductor fin each above an upper surface of the shared gate; and
growing first and second epitaxy regions from the first and second upper surfaces and across the shared gate from the first upper surface to the second upper surface so as to form the air gap between the shared epitaxy region and a surface of the shared gate to form a shared epitaxy region having an air gap between a lower epitaxy surface and the shared gate, the shared epitaxy region on a top surface of the first vertical semiconductor fin and a top surface of the second vertical semiconductor fin such that the shared gate is below the shared epitaxy region and is interposed between the shared epitaxy region and the doped region of the substrate;
forming a first contact in the first portion of the doped region; wherein the first contact is electrically coupled to a positive supply voltage; and
forming a second contact in the second portion of the doped region without forming a contact in the shared epitaxy region such that a current flows between the first contact and the second contact thereby forming a serial connection between the first contact, first vertical semiconductor fin, the second vertical semiconductor fin, and the second contact.