Scalable fir filter
A Scalable Finite Impulse Response (“SFIR”) filter is disclosed. The SFIR filter includes a pre-processing section, a post-processing section, and a finite impulse response (“FIR”) Matrix. The FIR Matrix includes a plurality of filter taps and a plurality of signal paths in signal communication with each filter tap. The plurality of signal paths are arranged to allow re-configurable data throughput between the each filter tap and the pre-processing section and post-processing section are in signal communication with the FIR Matrix.
1. A Scalable Finite Impulse Response (“SFIR”) filter comprising
a pre-processing section;
a post-processing section; and
a finite impulse response (“FIR”) Matrix coupled to the pre-processing section and the post-processing section, wherein the FIR Matrix includes:
a plurality of filter taps including a first filter tap, a second filter tap, and a third filter tap, the first filter tap configured to perform a first operation and to provide a first result of the first operation at an output of the first filter tap, the third filter tap configured to perform a second operation and to provide a second result of the second operation at an output of the third filter tap, and the second filter tap having a first input coupled to the output of the first filter tap and having a second input coupled to the output of the third filter tap; and
a plurality of signal paths arranged to allow re-configurable data throughput between each filter tap of the plurality of filter taps.
2. The SFIR filter of claim 1 , wherein the FIR Matrix further includes a fourth filter tap coupled to the output of the first filter tap and the output of the third filter tap.
3. The SFIR filter of claim 2 , wherein the second each filter tap includes:
a multiplexer coupled to the first input and to the second input,
a first flip-flop coupled to an output of the multiplexer,
a gain section,
a second flip-flop, and
an adder coupled to the gain section multiplier and the second flip-flop.
4. The SFIR filter of claim 3 , wherein the gain section includes a gain section multiplier and a coefficient section.
5. The SFIR filter of claim 4 , wherein each flip-flop, of the second filter tap, is a D flip-flop.
6. The SFIR filter of claim 3 , wherein the plurality of signal paths includes:
a first serial signal path from the first filter tap to the second filter tap,
a second serial signal path from the second filter tap to the third filter tap,
a first cross signal path from the first filter tap to the fourth filter tap,
a second cross signal path from the third filter tap to the second filter tap, and
a third serial signal path from the third filter tap to the fourth filter tap.
7. The SFIR filter of claim 6 , wherein:
the first serial signal path is a signal path from an output of a first filter tap multiplexer to an input of a second filter tap multiplexer,
the second serial signal path is a signal path from an output of the second filter tap multiplexer to an input of a third filter tap multiplexer,
the first cross signal path is a signal path from the output of the first filter tap multiplexer to an input of a fourth filter tap multiplexer,
the second cross signal path from an output of the third filter tap multiplexer to the input of the second filter tap multiplexer, and
the third serial signal path from the output of the third filter tap multiplexer to the input of the fourth filter tap multiplexer.
8. The SFIR filter of claim 7 , wherein the plurality of signal paths further includes:
a first adder signal path from a first filter tap adder to a second filter tap second flip-flop, and
a second adder signal path from a third filter tap adder to a fourth filter tap second flip-flop.
9. The SFIR filter of claim 8 , wherein the plurality of signal paths further includes:
a first pipeline data signal path from a first filter first flip-flop to the second filter tap second flip-flop through a first filter gain section multiplier and a first filter adder, and
a second pipeline data signal path from a third filter first flip-flop to the fourth filter tap second flip-flop through a third filter gain section multiplier and a third filter adder.
10. The SFIR filter of claim 9 , wherein the plurality of signal paths are arranged to configure the SFIR filter into a one serial input four tap filter or a two parallel input two tap filter.
11. The SFIR filter of claim 1 , wherein the SFIR filter is a type of filter chosen from the group consisting of a Hilbert transform filter, a decimator, an interpolator, a real FIR filter, a complex FIR filter, and an adaptive filter.
12. The SFIR filter of claim 1 , wherein the SFIR filter is configured to operate as a real FIR filter and includes the pre-processing section configured as a first pass-through device and the post-processing section configured as a second pass-through device.
13. The SFIR filter of claim 1 , wherein the SFIR filter is configured to operate as a complex FIR filter and includes the pre-processing section configured as a fan-out device and the post-processing section configured as a summation device.
14. The SFIR filter of claim 1 , wherein the SFIR filter is configured to operate as a decimator and includes the pre-processing section configured as a re-order device and the post-processing section configured as a summation device.
15. The SFIR filter of claim 1 , wherein the SFIR filter is configured to operate as an interpolator and includes the pre-processing section configured as a fan-out device and the post-processing section configured as a re-order device.
16. A Scalable Finite Impulse Response (“SFIR”) filter comprising:
means for pre-processing;
means for post-processing; and
a finite impulse response (“FIR”) filtering matrix coupled to the means for pre-processing and the means for post-processing, wherein the FIR filtering matrix includes:
a plurality of filter taps including a first filter tap, a second filter tap, and a third filter tap, the first filter tap configured to perform a first operation and to provide a first result of the first operation at an output of the first filter tap, the third filter tap configured to perform a second operation and to provide a second result of the second operation at an output of the third filter tap, and the second filter tap having a first input coupled to the output of the first filter tap and having a second input coupled to the output of the third filter tap; and
a plurality of signal paths, wherein the plurality of signal paths includes means to allow re-configurable data throughput between each filter tap of the plurality of filter taps.
17. An Application Specific Integrated Circuit (“ASIC”) comprising:
a Scalable Finite Impulse Response (“SFIR”) filter including:
a pre-processing section,
a post-processing section, and
a finite impulse response (“FIR”) Matrix coupled to the pre-processing section and the post-processing section, wherein the FIR Matrix includes:
a plurality of filter taps including a first filter tap, a second filter tap, and a third filter tap, the first filter tap configured to perform a first operation and to provide a first result of the first operation at an output of the first filter tap, the third filter tap configured to perform a second operation and to provide a second result of the second operation at an output of the third filter tap, and the second filter tap having a first input coupled to the output of the first filter tap and having a second input coupled to the output of the third filter tap; and
a plurality of signal paths filter tap of the plurality of filter taps.
18. The ASIC of claim 17 , wherein the second filter tap includes:
a multiplexer,
a first flip-flop coupled to an output of the multiplexer,
a gain section having a gain section multiplier and a coefficient section,
a second flip-flop, and
an adder coupled to the gain section and the second flip-flop.
19. The ASIC of claim 18 , wherein the FIR Matrix further includes a fourth filter tap, and
wherein the plurality of signal paths includes:
a first serial signal path from the first filter tap to the second filter tap,
a second serial signal path from the second filter tap to the third filter tap,
a first cross signal path from the first filter tap to the fourth filter tap,
a second cross signal path from the third filter tap to the second filter tap, and
a third serial signal path from the third filter tap to the fourth filter tap, and
wherein
the first serial signal path is a signal path from an output of a first filter tap multiplexer to an input of a second filter tap multiplexer,
the second serial signal path is a signal path from an output of the second filter tap multiplexer to an input of a third filter tap multiplexer,
the first cross signal path is a signal path from the output of the first filter tap multiplexer to an input of a fourth filter tap multiplexer,
the second cross signal path from an output of the third filter tap multiplexer to the input of the second filter tap multiplexer, and
the third serial signal path from the output of the third filter tap multiplexer to the input of the fourth filter tap multiplexer.
20. The ASIC of claim 19 , wherein the plurality of signal paths further includes:
a first adder signal path from a first filter tap adder to a second filter tap second flip-flop, and
a second adder signal path from a third filter tap adder to a fourth filter tap second flip-flop, and
wherein the plurality of signal paths further includes:
a first pipeline data signal path from a first filter first flip-flop to the second filter tap second flip-flop through a first filter gain section multiplier and a first filter adder, and
a second pipeline data signal path from a third filter first flip-flop to the fourth filter tap second flip-flop through a third filter gain section multiplier and a third filter adder.