Embedded variable gain amplifier in a current steering digital-to-analog converter
Apparatus and associated methods relating to a digital-to-analog converter (DAC) include a programmable resistance network coupled between a voltage supply node V DD and a switch cell circuit to provide a predetermined resistance in response to the V DD and current I S of the switch cell circuit. In an illustrative example, the DAC may include a switch cell circuit comprising one or more switch cells connected in parallel. Each switch cell may include a differential gain circuit having a first branch coupled to a second branch at an input of a current source. The programmable resistance may include a variable resistance configured to adjust a voltage (Vbias) supplied to the switch cell circuit in response to a control signal. By introducing the programmable resistance network, predetermined bias and/or gain values may be dynamically adjusted with a constant board-level power supply V DD .
1. A circuit comprising:
a switch cell circuit comprising at least one switch cell, each of the at least one switch cells comprising a differential gain circuit having a first branch coupled to a second branch at an input of a current source, the first branch and the second branch configured to combine their respective currents to supply a current amplitude of I DAC to the current source in response to a differential control signal;
a first differential resistance coupled to supply current from a bias node to the first branch of each of the at least one switch cells;
a second differential resistance coupled to supply current from the bias node to the second branch of each of the at least one switch cells; and,
a programmable resistance coupled between a voltage supply node V DD and the bias node, wherein the programmable resistance comprises a variable resistance configured to adjust a voltage (V bias ) at the bias node to one of a predetermined set of values in response to a variable resistance programming signal (VRPS).
2. The circuit of claim 1 , further comprising a control circuit configured to generate the VRPS in response to automatically determined circuit parameters.
3. The circuit of claim 2 , wherein the circuit parameters comprise the current amplitude of I DAC .
4. The circuit of claim 2 , wherein the circuit parameters further comprise a resistance value of the first differential resistance and a resistance value of the second differential resistance.
5. The circuit of claim 2 , wherein the control circuit is further configured to generate the VRPS in response to a lookup table storing one or more predetermined settings for the VRPS.
6. The circuit of claim 1 , further comprising a control circuit configured to generate the VRPS in response to predetermined gain specification for a digital-to-analog Converter (DAC).
7. The circuit of claim 1 , further comprising a capacitance arranged in a parallel configuration with at least a portion of the programmable resistance.
8. The circuit of claim 1 , wherein the programmable resistance comprises a network of resistive paths configured to be selectively controlled in response to the VRPS.
9. The circuit of claim 8 , wherein the network of resistive paths comprises one or more p-channel FETs.
10. The circuit of claim 1 , further comprising a first programmable differential resistance coupled in parallel with the first differential resistance, wherein the first programmable differential resistance comprises a first variable resistance configured to adjust a differential gain of the first branch to a first predetermined gain value in response to a first variable differential resistance programming signal (VDRPS).
11. The circuit of claim 10 , further comprising a second programmable differential resistance coupled in parallel with the second differential resistance, wherein the second programmable differential resistance comprises a second variable resistance configured to adjust the differential gain of the second branch to a second predetermined gain value in response to a second variable differential resistance programming signal (VDRPS).
12. The circuit of claim 1 , further comprising a plurality of the at least one switch cell connected in parallel.
13. The circuit of claim 12 , wherein the plurality of the at least one switch cell connected in parallel comprises switch cells between 1 and 128.
14. A method comprising:
combining, with a switch cell circuit, respective currents from a first branch and a second branch to supply a current amplitude I DAC to a current source in response to a differential control signal, wherein the switch cell circuit comprising at least one switch cell, each of the at least one switch cells comprising a differential gain circuit having the first branch coupled to the second branch at an input of the current source;
supplying current from a bias node to the first branch of each of the at least one switch cells through a first differential resistance;
supplying current from the bias node to the second branch of each of the at least one switch cells through a second differential resistance; and,
adjusting a voltage (V bias ) at the bias node to one of a predetermined set of values in response to a variable resistance programming signal (VRPS) through a programmable resistance coupled between a voltage supply node V DD and the bias node,
wherein the programmable resistance comprises a variable resistance configured to adjust the voltage V bias at the bias node.
15. The method of claim 14 , further comprising generating the VRPS in response to automatically determined circuit parameters.
16. The method of claim 15 , wherein the circuit parameters comprise the current amplitude of I DAC .
17. The method of claim 16 , wherein the circuit parameters further comprise a resistance value of the first differential resistance and a resistance value of the second differential resistance.
18. The method of claim 14 , wherein the first differential resistance is programmable.
19. The method of claim 18 , wherein the second differential resistance is programmable.
20. The method of claim 14 , wherein the switch cell circuit further comprises a plurality of the at least one switch cell connected in parallel.