Noise cancellation system
A noise cancellation system comprises a first noise cancellation apparatus configured to process an I-channel signal, wherein an I-channel differential mode second-order intermodulation component and an I-channel common mode second-order intermodulation component cancel each other in the first noise cancellation apparatus and a second noise cancellation apparatus configured to process a Q-channel signal, wherein a Q-channel differential mode second-order intermodulation component and a Q-channel common mode second-order intermodulation component cancel each other in the second noise cancellation apparatus.
1. A system comprising:
a noise correction circuit configured to receive a radio frequency signal through a mixer, wherein the noise correction circuit comprises:
an amplifier stage configured to provide amplification of the radio frequency signal received at a first drain/source terminal of first and second FET transistors, and generate an output signal at a second drain/source terminal of the first and second FET transistors, wherein the output signal is produced at two output terminals of the amplifier stage;
a second-order noise reduction stage connected between the two output terminals of the amplifier stage, wherein the second-order noise reduction stage is configured such that differential mode noise and common mode noise cancel each other; and
a feedback loop stage connected in parallel with the second-order noise reduction stage between the two output terminals of the amplifier stage; and
an amplifier connected in series with the noise correct circuit.
2. The system of claim 1 , wherein the second-order noise reduction stage comprises:
a first adjustable resistor and a second adjustable resistor connected in series between the two output terminals of the amplifier stage, and wherein a common node of the first adjustable resistor and the second adjustable resistor is connected to an output of a buffer, and wherein a first input of the buffer is connected to a reference voltage and a second input of the buffer is connected to the output of the buffer.
3. The system of claim 2 , wherein:
the first adjustable resistor comprises a first fixed portion and a first adjustable portion; and
the second adjustable resistor comprises a second fixed portion and a second adjustable portion, and wherein:
the first fixed portion is of a resistance value equal to that of the second fixed portion; and
the first adjustable portion and the second adjustable portion are equal and have opposite directions.
4. The system of claim 2 , wherein:
the reference voltage is used as a reference of the feedback loop stage, and wherein a voltage across the two output terminals of the amplifier stage is adjustable by adjusting the reference voltage.
5. The system of claim 2 , wherein:
the buffer is configured to regulate a voltage at the common node of the first adjustable resistor and the second adjustable resistor approximately equal to the reference voltage.
6. The system of claim 1 , wherein:
the amplifier stage is a trans-impedance amplifier stage comprising a common-gate trans-impedance amplifier, and wherein the common-gate trans-impedance amplifier comprises two common gate transistors.
7. The system of claim 1 , wherein:
the amplifier comprises an adjustable resistor for providing adjustable amplification of the radio frequency signal.
8. The system of claim 1 , wherein:
the feedback loop stage is configured to regulate an output voltage of the amplifier stage.
9. The system of claim 1 , wherein the feedback loop stage comprises:
a detector circuit coupled to an output of the amplifier stage; and
an operation amplifier configured to regulate a dc output of the amplifier stage.
10. The system of claim 9 , wherein the detector circuit comprises:
a first resistor and a second resistor connected in series between two output terminals of the output of the amplifier stage, and wherein a common node of the first resistor and the second resistor is connected to an input of the operation amplifier.
11. An apparatus comprising:
an amplifier stage configured to provide amplification of a radio frequency signal and generate a positive output signal at a first output terminal and a negative output signal at a second output terminal;
a second-order noise reduction stage connected between two output terminals of the amplifier stage, wherein the second-order noise reduction stage comprises a first adjustable resistor and a second adjustable resistor connected in series between the first output terminal and the second output terminal of the amplifier stage, and wherein the second-order noise reduction stage is configured such that differential mode noise and common mode noise cancel each other; and
a feedback loop stage connected in parallel with the second-order noise reduction stage between the two output terminals of the amplifier stage, wherein the feedback loop stage comprises a first resistor and a second resistor connected in series between the first output terminal and the second output terminal of the amplifier stage.
12. The apparatus of claim 11 , wherein:
the feedback loop stage is configured to regulate an output voltage of the amplifier stage.
13. The apparatus of claim 11 , wherein:
the amplifier stage and the second-order noise reduction stage are connected in parallel.
14. The apparatus of claim 11 , wherein:
the first adjustable resistor and the second adjustable resistor are configured such that an absolute value of a first resistance variation of the first adjustable resistor is equal to an absolute value of a second resistance variation of the second adjustable resistor.
15. The apparatus of claim 11 , wherein:
the amplifier stage is a trans-impedance stage comprising two common gate transistors.
16. A system comprising:
a trans-impedance stage configured to provide amplification of a radio frequency signal;
a noise reduction stage connected to the trans-impedance stage, wherein the noise reduction stage comprises a first adjustable resistor and a second adjustable resistor connected in series, and a common node of the first adjustable resistor and the second adjustable resistor is connected to an output of a buffer, the buffer having a first input connected to a predetermined reference voltage and a second input connected to the output of the buffer, and wherein the noise reduction stage is configured such that differential mode noise and common mode noise cancel each other; and
a feedback loop stage connected in parallel with the noise reduction stage between two output terminals of the trans-impedance stage, wherein the feedback loop stage is configured to regulate an output voltage of the trans-impedance stage.
17. The system of claim 16 , wherein:
the noise reduction stage is a second-order noise reduction stage configured to attenuate second-order intermodulation noise.
18. The system of claim 16 , wherein:
the trans-impedance stage comprises two common gate transistors; and
the first adjustable resistor and the second adjustable resistor are configured such that an absolute value of a first resistance variation of the first adjustable resistor is equal to an absolute value of a second resistance variation of the second adjustable resistor.
19. The system of claim 18 , wherein:
the buffer is configured to regulate a voltage at the common node of the first adjustable resistor and the second adjustable resistor equal to the predetermined reference voltage.