Integrated circuit devices including a vertical memory device
Provided is an integrated circuit device including a plurality of word lines overlapping each other, in a vertical direction, on a substrate, a plurality of channel structures extending in the vertical direction through the plurality of word lines on an area of the substrate, a plurality of bit line contact pads on the plurality of channel structures, and a plurality of bit lines, wherein the plurality of bit lines include a plurality of first bit lines extending parallel to each other at a first pitch in a center region of the area, and a plurality of second bit lines extending at a second pitch in an edge region of the area, the second pitch being different from the first pitch.
1. An integrated circuit device comprising:
a plurality of word lines extending parallel to a main surface of a substrate and overlapping each other in a vertical direction, on the substrate;
a plurality of channel structures extending in the vertical direction through the plurality of word lines on an area of the substrate; and
a plurality of bit lines connected to the plurality of channel structures on the area,
wherein the plurality of bit lines comprise:
a plurality of first bit lines arranged at a first pitch in a center region of the area; and
a plurality of second bit lines arranged at a second pitch in an edge region of the area, the second pitch being different from the first pitch.
2. The integrated circuit device of claim 1 , wherein the first pitch is a constant pitch and the second pitch is a variable pitch.
3. The integrated circuit device of claim 1 , wherein separation distances between adjacent ones of the plurality of second bit lines increase with increasing distance from the center region of the area.
4. The integrated circuit device of claim 1 , wherein the plurality of first bit lines extend lengthwise linearly, and at least one of the plurality of second bit lines extends lengthwise nonlinearly.
5. The integrated circuit device of claim 1 , wherein the plurality of channel structures comprise:
a plurality of first channel structures arranged at a third pitch in the center region of the area; and
a plurality of second channel structures arranged at a fourth pitch in the edge region of the area, the fourth pitch being different from the third pitch.
6. The integrated circuit device of claim 1 , wherein the plurality of channel structures comprise:
a plurality of first channel structures arranged at a constant pitch in the center region of the area; and
a plurality of second channel structures arranged at a variable pitch in the edge region of the area.
7. The integrated circuit device of claim 1 , wherein the plurality of channel structures comprise:
a plurality of first channel structures arranged in the center region of the area; and
a plurality of second channel structures arranged in the edge region of the area, at least one of the plurality of second channel structures nonlinearly extending in the vertical direction.
8. The integrated circuit device of claim 1 , wherein at least one of the plurality of second bit lines comprises a convex curved portion in a direction away from the center region of the area.
9. The integrated circuit device of claim 1 , wherein at least one of the plurality of second bit lines comprises a convex curved portion in a direction toward the center region of the area.
10. The integrated circuit device of claim 1 , wherein the plurality of second bit lines comprise a convex curved portion, and
wherein a plurality of separation distances between adjacent ones of the plurality of second bit lines comprise a first separation distance regardless of a distance from the center region of the area, and a plurality of second separation distances that increase with increasing distance from the center region of the area.
11. An integrated circuit device comprising:
a plurality of word lines extending parallel to a main surface of a substrate and overlapping each other in a vertical direction, on the substrate;
a plurality of channel structures extending in the vertical direction through the plurality of word lines on an area of the substrate; and
a plurality of bit lines connected to the plurality of channel structures on the area,
wherein the plurality of channel structures comprise:
a plurality of first channel structures arranged at a first pitch in a center region of the area in a first horizontal direction, the first horizontal direction crossing a longitudinal direction of the plurality of bit lines; and
a plurality of second channel structures arranged at a second pitch in an edge region of the area in the first horizontal direction, the second pitch being different from the first pitch.
12. The integrated circuit device of claim 11 , wherein the first pitch is a constant pitch and the second pitch is a variable pitch.
13. The integrated circuit device of claim 11 , wherein a plurality of separation distances between adjacent ones of the plurality of second channel structures increase with increasing distance from the center region of the area.
14. The integrated circuit device of claim 11 , wherein at least one of the plurality of second channel structures nonlinearly extends in the vertical direction.
15. The integrated circuit device of claim 11 , wherein the plurality of bit lines comprise:
a plurality of first bit lines arranged at a constant pitch in the center region of the area; and
a plurality of second bit lines arranged at a variable pitch in the edge region of the area.
16. The integrated circuit device of claim 11 , wherein separation distances between adjacent ones of the plurality of bit lines in the edge region of the area increase with increasing distance from the center region of the area.
17. The integrated circuit device of claim 11 , wherein the plurality of bit lines comprise:
a plurality of first bit lines extending lengthwise linearly in the center region of the area; and
a plurality of second bit lines extending lengthwise nonlinearly in the edge region of the area.
18. The integrated circuit device of claim 11 , wherein the plurality of bit lines comprise:
a plurality of first bit lines arranged in the center region of the area; and
a plurality of second bit lines arranged in the edge region of the area, at least one of the plurality of second bit lines comprising a convex curved portion.
19. An integrated circuit device comprising:
a plurality of word lines extending parallel to a main surface of a substrate and overlapping each other in a vertical direction, on the substrate;
a plurality of channel structures extending in the vertical direction through the plurality of word lines on an area of the substrate; and
a plurality of bit lines connected to the plurality of channel structures on the area,
wherein the plurality of bit lines comprise:
a plurality of first bit lines arranged at a constant pitch in a center region of the area; and
a plurality of second bit lines arranged at a variable pitch in an edge region of the area, and
wherein at least one of the plurality of channel structures extends nonlinearly in the vertical direction in the edge region of the area.
20. The integrated circuit device of claim 19 , wherein the plurality of first bit lines extend lengthwise linearly, and at least one of the plurality of second bit lines extends lengthwise nonlinearly.