Master-slave flip flop

1. A master-slave flip flop comprising a master latch and a slave latch which are sequentially disposed on a substrate in a first direction,

wherein the master latch includes a first NMOS transistor and a first PMOS transistor each gated by a first clock signal, and the first NMOS transistor and the first PMOS transistor share a first gate line extending in a second direction intersecting with the first direction, and

the slave latch includes a second NMOS transistor and a second PMOS transistor each gated by the first clock signal, and the second NMOS transistor and the second PMOS transistor share a second gate line extending in the second direction.

2. The master-slave flip flop of claim 1 ,

wherein the master latch further comprises:

a third PMOS transistor which is gated by a second clock signal obtained by inverting the first clock signal and shares a drain region with the first PMOS transistor; and

a third NMOS transistor which is gated by the second clock signal and shares a drain region with the first NMOS transistor, and

the slave latch further comprises:

a fourth PMOS transistor which is gated by the second clock signal and shares a drain region with the second PMOS transistor; and

a fourth NMOS transistor which is gated by the second clock signal and shares a drain region with the second NMOS transistor.

3. The master-slave flip flop of claim 2 , wherein the third PMOS transistor includes a third gate line extending in the second direction, and

the third NMOS transistor includes a fourth gate line extending in the second direction.

4. The master-slave flip flop of claim 3 , wherein the third gate line is disposed on one side of the first gate line, and the fourth gate line is disposed on the other side of the first gate line.

5. The master-slave flip flop of claim 4 , wherein the substrate has a first active region in which the first PMOS transistor is formed, and a second active region in which the first NMOS transistor is formed, and

the third gate line does not overlap the second active region, and the fourth gate line does not overlap the first active region.

6. The master-slave flip flop of claim 2 , wherein the fourth PMOS transistor includes a third gate line extending in the second direction, and

the fourth NMOS transistor includes a fourth gate line extending in the second direction.

7. The master-slave flip flop of claim 6 , wherein the third gate line and the fourth gate line are not aligned in the second direction.

8. The master-slave flip flop of claim 2 , further comprising:

an inverter,

wherein the first clock signal is directly input from a clock signal terminal without passing through the inverter, and

the inverter inverts the first clock signal to output the second dock signal.

9. The master-slave flip flop of claim 1 , further comprising:

a first fin and a second fin formed to protrude from the substrate and extending in the first direction,

wherein the first PMOS transistor is a fin-type transistor formed by intersection of the first gate line and the first fin, and

the first NMOS transistor is a fin-type transistor formed by intersection of the first gate line and the second fin.

10. A master-slave flip flop comprising a first master slave circuit and a second master slave circuit which share a first clock signal,

wherein the first master slave circuit includes a first master latch and a first slave latch disposed on a substrate sequentially in a first direction,

the second master slave circuit includes a second master latch and a second slave latch disposed on the substrate sequentially in the first direction,

the first master latch includes a first NMOS transistor and a first PMOS transistor each gated by the first clock signal, and the first NMOS transistor and the first PMOS transistor share a first gate line extending in a second direction intersecting with the first direction,

the second master latch includes a second PMOS transistor and a second NMOS transistor which share the first gate line and are each gated by the first clock signal,

the first slave latch includes a third NMOS transistor and a third PMOS transistor each gated by the first clock signal, and the third NMOS transistor and the third PMOS transistor share a second gate line extending in the second direction, and

the second slave latch includes a fourth PMOS transistor and a fourth NMOS transistor which share the second gate line and are each gated by the first clock signal.

11. The master-slave flip flop of claim 10 , wherein the first master latch and the second master latch are disposed side by side in the first direction.

12. The master-slave flip flop of claim 10 , Wherein the first slave latch includes a fifth NMOS transistor including a third gate line extending in the second direction on one side of the second gate line, and

the second slave latch includes a sixth NMOS transistor sharing the third gate line, and the fifth NMOS transistor and the sixth NMOS transistor are aligned in the second direction.

13. The master-slave flip flop of claim 10 , wherein the first master latch includes a fifth NMOS transistor including a third gate line extending in the second direction on one side of the first gate line, and

the second master latch includes a sixth NMOS transistor sharing the third gate line, and the fifth NMOS transistor and the sixth NMOS transistor are aligned in the second direction.

14. The master-slave flip flop of claim 13 , wherein the first master latch further includes a fifth PMOS transistor including a fourth gate line extending in the second direction on the other side of the first gate line,

the second master latch further includes a sixth PMOS transistor including a fifth gate line extending in the second direction on the other side of the first gate line, and

the fourth gate line and the fifth gate line are aligned in the second direction.

15. The master-slave flip flop of claim 14 , wherein the fourth gate line and the fifth gate line are connected to each other, and

the fifth PMOS transistor and the sixth PMOS transistor share the fourth gate line and the fifth gate line connected to each other.

16. The master-slave flip flop of claim 10 , further comprising:

an inverter,

wherein the first clock signal is directly input from a clock signal terminal without passing through the inverter, and

the inverter inverts the first clock signal to output a second clock signal.

17. A master-slave flip flop comprising a master latch and a slave latch which are disposed side by side in a second direction intersecting with a first direction and share a first power rail and a second power rail, on a substrate including a first active region and a second active region each extending in the first direction and spaced apart from each other in the second direction,

wherein the master latch includes:

a first gate line extending in the second direction;

a first transistor formed by overlap of the first gate line and the first active region; and

a second transistor formed by overlap of the first gate line and the second active region, and

the slave latch includes:

a second gate line extending in the second direction;

a third transistor formed by overlap of the second gate line and the first active region; and

a fourth transistor formed by overlap of the second gate line and the second active region.

18. The master-slave flip flop of claim 17 , wherein the master latch further comprises:

a third gate line which extends in the second direction on one side of the first gate line and overlaps the first active region to form a fifth transistor; and

a fourth gate line which extends in the second direction on the other side of the first gate line and overlaps the second active region to form a sixth transistor.

19. The master-slave flip flop of claim 18 , wherein the third gate line does not overlap the second active region, and

the fourth gate line does not overlap the first active region.

20. The master-slave flip flop of claim 17 , wherein the slave latch comprises:

a third gate line which extends in the second direction on one side of the second gate line and overlaps the first active region to form a fifth transistor; and

a fourth gate line which extends in the second direction on the other side of the first gate line and overlaps the second active region to form a sixth transistor.