IP Library Granted Patent US 10,592,632
Granted Patent B2
US 10,592,632 · App. 15/957,409 · Granted Mar 17, 2020

Method for analyzing design of an integrated circuit

Inventors: Ryan Ryoung han Kim (Bertem, BE); Jae Uk Lee (Heverlee, BE)
Assignee: Imec vzw
G06F17/5081G03F7/70433G06F17/5072G06N3/088G06T7/0006G06F3/147G06T2207/20021G06T2207/20056G06T2207/20081G06T2207/20084G06T2207/30148
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Quick Facts
Patent No.
US 10,592,632
App. No.
15/957,409
Granted
Mar 17, 2020
Kind
B2
Abstract

Methods and systems for analyzing design of an integrated circuit are described. An example method includes receiving a design layout for an integrated circuit and forming a plurality of images of portions of the design layout. The method also includes, for each image of a portion of the design layout, calculating a Fourier transform representation of the image and extracting values of pre-defined parameters from the Fourier transform representation. The method also includes comparing the extracted parameter values of the plurality of images to create a clustering model by unsupervised machine learning and to sort each image of a portion of the design layout into a cluster defined by the clustering model. The method also includes determining a number of images sorted into at least one cluster defined by the clustering model.

Claims (49)

1. A method for analyzing design of an integrated circuit, the method comprising:

receiving a design layout for an integrated circuit;

forming a plurality of images of portions of the design layout, and for each image of a portion of the design layout:

calculating a Fourier transform representation of the image; and

extracting values of pre-defined parameters from the Fourier transform representation;

comparing the extracted values of pre-defined parameters of the plurality of images to create a clustering model by unsupervised machine learning and to sort each image of a portion of the design layout into a cluster defined by the clustering model;

determining a number of images sorted into at least one cluster defined by the clustering model; and

calculating at least one quality score of the design layout based on the clustering model and the determined number of images sorted into the at least one cluster.

2. The method according to claim 1 , wherein the at least one quality score is based on a number of clusters in the clustering model and a density value of a determined number of images in each cluster.

3. The method according to claim 1 , further comprising:

comparing the at least one quality score to at least one pre-defined threshold; and

based on a result of the comparison, outputting a recommendation to re-design the design layout for the integrated circuit.

4. The method according to claim 1 , further comprising outputting the determined number of images for presentation in a diagram on a display.

5. The method according to claim 1 , further comprising:

reconstructing an image based on the extracted values of pre-defined parameters by calculating an inverse Fourier transform using the extracted values of pre-defined parameters; and

outputting the reconstructed image for presentation on a display.

6. The method according to claim 1 , wherein comparing the extracted values of pre-defined parameters comprises applying different parameter weights for different parameters, and wherein the method further comprises:

receiving input for changing parameter weights and repeating comparing the extracted values of pre-defined parameters based on the different parameter weights.

7. The method according to claim 1 , wherein calculating a Fourier transform representation of the image comprises forming at least one envelope along a cross-sectional direction intersecting origin of a two-dimensional Fourier transform of the image.

8. The method according to claim 7 , wherein the pre-defined parameters include at least one in the group of: a zeroth order intensity of the at least one envelope, a first order intensity of the at least one envelope, and a distance between a peak of the zeroth order and a peak of the first order of the at least one envelope.

9. The method according to claim 1 , wherein forming of a plurality of images of portions of the design layout comprises forming a binary image of a layer of the design layout.

10. The method according to claim 9 , wherein forming of a plurality of images of portions of the design layout further comprises cutting the binary image into a plurality of images of portions of the binary image.

11. The method according to claim 10 , wherein cutting the binary image into a plurality of images of portions of the binary image forms overlapping images with a size of the images being dependent on the layer of the design layout.

12. The method according to claim 10 , wherein forming of a plurality of images of portions of the design layout further comprises enlarging a size of a cut image by zero-padding.

13. A computer program product comprising a non-transitory computer-readable medium having computer-readable instructions stored thereon that, in response to execution by a processing unit, cause the processing unit to perform operations, the instructions comprising:

instructions for receiving a design layout for an integrated circuit;

instructions for forming a plurality of images of portions of the design layout, and for each image of a portion of the design layout:

(i) calculating a Fourier transform representation of the image; and

(ii) extracting values of pre-defined parameters from the Fourier transform representation;

instructions for comparing the extracted values of pre-defined parameters of the plurality of images to create a clustering model by unsupervised machine learning and to sort each image of a portion of the design layout into a cluster defined by the clustering model;

instructions for determining a number of images sorted into at least one cluster defined by the clustering model; and

instructions for calculating at least one quality score of the design layout based on the clustering model and the determined number of images sorted into the at least one cluster.

14. A device for designing of an integrated circuit, the device comprising:

a processing unit configured to execute processing instructions to implement:

a design tool for designing a layout for an integrated circuit and outputting a design layout; and

a design analytics tool, wherein the design analytics tool is configured to:

receive a design layout for an integrated circuit;

form a plurality of images of portions of the design layout, and for each image of a portion of the design layout:

calculate a Fourier transform representation of the image; and

extract values of pre-defined parameters from the Fourier transform representation;

compare the extracted values of pre-defined parameters of the plurality of images to create a clustering model by unsupervised machine learning and to sort each image of a portion of the design layout into a cluster defined by the clustering model;

determine a number of images sorted into each cluster defined by the clustering model; and

calculate at least one quality score of the design layout based on the clustering model and the determined number of images sorted into each cluster.

15. The device of claim 14 , further comprising:

an input module configured to receive instructions for controlling the design tool and the design analytics tool.

16. The device of claim 14 , further comprising:

a display configured to output the determined number of images for presentation in a diagram.

17. The device of claim 16 , wherein the design analytics tool is further configured to reconstruct an image based on the extracted values of pre-defined parameters by calculating an inverse Fourier transform using the extracted values of pre-defined parameters, and wherein the display is further configured to output the reconstructed image.

18. The device of claim 14 , wherein the at least one quality score is based on a number of clusters in the clustering model and a density value of a determined number of images in each cluster.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2018
From: KIM, RYAN RYOUNG HAN; LEE, JAE UK
To: IMEC VZW
Reel/Frame 045620/0309 →
Priority Claims (1)
EP 17167587 · Apr 21, 2017 · regional
Continuity (1)
Related Publication 20180307792A1 · Oct 25, 2018