IP Library › Granted Patent US 10,593,617
Granted Patent B2
US 10,593,617 · App. 15/910,425 · Granted Mar 17, 2020

Semiconductor device

Inventors: Hiroshi Ashikaga (Kawasaki Kanagawa, JP); Naoki Kimura (Ebina Kanagawa, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L23/49838H01L23/49816H01L23/49827H01L23/544H01L25/0655H01L23/3128H01L24/16H01L2223/54433H01L2223/54486H01L2224/131H01L2224/16225H01L2224/16235H01L2224/32225H01L2224/73204H01L2224/92125H01L2924/15311H01L2924/3511
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Quick Facts
Patent No.
US 10,593,617
App. No.
15/910,425
Filed
Mar 2, 2018
Granted
Mar 17, 2020
Kind
B2
Art Unit
2811
USPC
257/668
Abstract

According to one embodiment, a semiconductor device includes a first board including a plurality of terminals, a semiconductor chip flip-chip mounted to the first board, and an insulating layer covering the first board and the semiconductor chip. The plurality of terminals include at least one first terminal electrically connected to the semiconductor chip, and at least one second terminal that is not connected to the semiconductor chip, wherein the at least one second terminal is not covered by the insulating layer.

Claims (60)

1. A semiconductor device, comprising:

a first board including a plurality of vias;

a semiconductor chip flip-chip mounted to the first board;

an insulating layer covering the first board and the semiconductor chip; and

a second board electrically connected to the first board and including a ground terminal thereon, wherein

the plurality of vias include a first via electrically connected to the semiconductor chip; and a second via that is not electrically connected to the semiconductor chip,

the insulating layer includes an opening at a position above the second via, the second via is not covered by the insulating layer, and a conductive portion is disposed in the opening of the insulating layer,

an upper surface of the conductive portion is flush with an upper surface of the insulating layer, and

the conductive portion has a thickness less than a thickness of the semiconductor chip above the first board and is electrically connected to the ground terminal of the second board through the second via.

2. The semiconductor device according to claim 1 , wherein the first board is rectangular, and

the second via is located adjacent to a corner of the first board.

3. The semiconductor device according to claim 1 , further comprising:

a conductive sheet disposed over the insulating layer.

4. The semiconductor device according to claim 3 , wherein the conductive sheet includes a label including information concerning the semiconductor device.

5. The semiconductor device according to claim 1 , wherein

the plurality of vias include a plurality of second vias that are not electrically connected to the semiconductor chip, the plurality of second vias including the second via, and

the conductive portion in the opening of the insulating layer is electrically connected to the ground terminal of the second board through the plurality of second vias.

6. The semiconductor device according to claim 1 , wherein the second via is one of the plurality of vias that is provided at an outermost position in a direction along a surface of the first board.

7. A semiconductor device, comprising:

a first board including a ground terminal; and

a first semiconductor component mounted on the first board, wherein

the first semiconductor component comprises:

a second board having a plurality of vias;

a semiconductor chip flip-chip mounted to the second board; and

an insulating layer covering the second board and the semiconductor chip, wherein

the plurality of vias of the second board include:

a first via electrically connected to the semiconductor chip; and

a second via that is not electrically connected to the semiconductor chip,

the insulating layer includes an opening at a position above the second via, the second via is not covered with the insulating layer, and a conductive portion is disposed in the opening of the insulating layer,

an upper surface of the conductive portion is flush with an upper surface of the insulating layer, and

the conductive portion has a thickness less than a thickness of the semiconductor chip above the second board and is electrically connected to the ground terminal of the first board through the second via.

8. The semiconductor device according to claim 7 , wherein

the second board has a rectangular shape having corners, and

the second via is located adjacent to one of the corners of the second board.

9. The semiconductor device according to claim 7 , wherein:

the first board comprises a ground layer, and a plurality of third vias connected to the ground layer; and

the second via is electrically connected to the ground layer through one of the third vias of the first board.

10. The semiconductor device according to claim 9 , further comprising:

a second semiconductor component mounted on the first board; and

a conductive layer covering the first semiconductor component and the second semiconductor component.

11. The semiconductor device according to claim 10 , wherein the conductive layer comprises a label on which information concerning the semiconductor device is provided.

12. The semiconductor device according to claim 11 , wherein:

a ground terminal of the first semiconductor component is connected to the ground layer at a first point through an interconnect on the first board;

a ground terminal of the second semiconductor component is connected to the ground layer at a second point through an interconnect on the first board; and

a distance between the first point and the second point is greater than a distance between a third point just below the ground terminal of the first semiconductor component on the ground layer and a fourth point just below the ground terminal of the second semiconductor component on the ground layer.

13. The semiconductor device according to claim 7 , wherein

the plurality of vias include a plurality of second vias that are not electrically connected to the semiconductor chip, the plurality of second vias including the second via, and

the conductive portion in the opening of the insulating layer is electrically connected to the ground terminal of the first board through the plurality of second vias.

14. The semiconductor device according to claim 7 , wherein the second via is one of the plurality of vias that is provided at an outermost position in a direction along a surface of the second board.

15. A semiconductor device, comprising:

a first board comprising a first surface, a second surface, and a body extending therebetween bounded by a perimeter, a first conductive path extending therethrough in a first region of the board and a second conductive path extending therethrough in a second region of the board;

a semiconductor chip flip-chip mounted over the first region of the first surface of the first board, wherein the semiconductor chip is electrically connected to the first conductive path;

a coating covering the semiconductor chip and the first surface of the first board in a region where the semiconductor chip is not mounted thereover; and

a first conductor extending through the coating and in electric contact with the second conductive path in the second region, wherein a surface of the first conductor spaced from the first surface of the first board is exposed at and flush with a surface of the coating spaced from the first surface of the first board, the first conductor has a thickness less than a thickness of the semiconductor chip, and the first conductor is electrically connected to ground through the second conductive path.

16. The semiconductor device according to claim 15 , wherein the first conductor is disposed over the second region of the first board.

17. The semiconductor device according to claim 16 , wherein the surface of the first conductor spaced from the first surface of the first board is coplanar with, or extends outwardly from, the surface of the coating spaced from the first surface of the first board.

18. The semiconductor device according to claim 17 , further comprising a conductive layer overlying the surface of the coating spaced from the first surface of the first board and contacting the surface of the first conductor spaced from the first surface of the first board.

19. The semiconductor device according to claim 15 , wherein

a plurality of second conductive paths, including the second conductive path, extend through the body of the first board in the second region, and

the first conductor is electrically connected to ground through the plurality of second conductive paths.

Assignments (4)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 21, 2018
From: ASHIKAGA, HIROSHI; KIMURA, NAOKI
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 045859/0967 →
Priority Claims (1)
JP 2017-179056 · Sep 19, 2017 · national
Continuity (1)
Related Publication 20190088583A1 · Mar 21, 2019
Cited By (8)
US 12,189,347 US 12,259,690 US 12,282,302 US 12,307,047 US 12,326,697 US 12,346,070 US 12,596,334 US 12,669,784