Scheme to align LDMOS drain extension to moat
An integrated circuit and method having an extended drain MOS transistor, wherein a diffused drain is deeper under a field oxide element in the drain than in a drift region under the gate. A field oxide hard mask layer is etched to define a drain field oxide trench area. Drain dopants are implanted through the drain field oxide trench area and a thermal drain drive is performed. Subsequently, the drain field oxide element is formed.
1. An extended drain metal oxide semiconductor (EDMOS) transistor, comprising:
a substrate having a surface;
a drain field oxide element and an adjacent field oxide element extending into the substrate from the surface;
a gate above the surface and extending partially over the drain field oxide element;
a drain contact region located between the drain field oxide element and the adjacent field oxide element, the adjacent field oxide element having a bottom surface and a sidewall surface abutting the drain contact region, and the drain contact region abutting the drain field oxide element on a side opposite from the gate;
a drain region including a drain p-n junction between the drain region and the substrate, wherein under the drain field oxide element the drain p-n junction has a first junction depth below the substrate surface and under the drain contact region the drain p-n junction has a second junction depth below the substrate surface, the first junction depth being greater than the second junction depth, and the p-n junction extending laterally no further than a corner formed by the bottom surface and the sidewall surface of the adjacent field oxide element.
2. The EDMOS transistor of claim 1 , further comprising a gate dielectric, a first portion of the gate dielectric being located directly on the drain region and a second portion of the gate dielectric being located directly on the substrate surface.
3. The EDMOS transistor of claim 1 , wherein the drain contact region abuts the adjacent field oxide element.
4. The EDMOS transistor of claim 1 , wherein the drain region terminates at the adjacent field oxide element.
5. The EDMOS transistor of claim 1 , wherein a surface of the drain field oxide element is coplanar with a surface of a gate dielectric located between the gate and the drain region.
6. The EDMOS transistor of claim 1 , further comprising a dielectric liner located between the drain field oxide element and the drain region.
7. The EDMOS transistor of claim 6 , wherein the dielectric liner is located between the drain field oxide element and a gate dielectric located between the gate and the drain region.
8. The EDMOS transistor of claim 1 , further comprising a sidewall dielectric on each side of the gate.
9. The EDMOS transistor of claim 1 , wherein the drain field oxide element is about centered laterally in the drain region.
10. The EDMOS transistor of claim 1 , wherein the drain region comprises arsenic.
11. The EDMOS transistor of claim 1 , wherein the drain region comprises phosphorous.
12. The EDMOS transistor of claim 1 , wherein the drain region comprises boron.
13. The EDMOS transistor of claim 1 , wherein the drain region comprises gallium.
14. The EDMOS transistor of claim 1 , wherein the drain region is n-type.
15. The EDMOS transistor of claim 1 , wherein the substrate comprises silicon.
16. The EDMOS transistor of claim 1 , further comprising a gate dielectric between the gate and the substrate, wherein the drain p-n junction intersects the substrate surface under the gate dielectric.