Method and apparatus of dynamic parallelism for controlling power consumption of SSDs

1. A method for adaptive power reduction for a solid-state storage device to dynamically control power consumption, the method comprising:

receiving a power limit command from a host at the solid-state storage device, the solid-state storage device including a plurality of processors, a memory and a plurality of nonvolatile memory devices;

receiving power consumption feedback;

using the power limit command and the power consumption feedback to calculate a new degree of parallelism for the solid-state storage device;

using the new degree of parallelism to control power consumption of the solid-state storage device to be within an allowed power budget over a given time window by controlling one or more of: i) processor parallelism, including activation of different numbers of processors within the solid-state storage device, ii) memory parallelism, including memory pool length for the memory of the solid-state storage device; and iii) nonvolatile memory parallelism, including activation of different numbers of nonvolatile memory devices within the solid-state storage device;

wherein the using the new degree of parallelism to control the one or more of the processor parallelism, memory parallelism and nonvolatile memory parallelism further includes providing a control signal to a voltage regulator to cause a voltage manager to output a different voltage to one or more of the processors, the memory and the nonvolatile memory devices; and

wherein the method is performed by a control circuit operating within the solid-state storage device, but external to the nonvolatile memory array.

2. The method of claim 1 , further comprising:

responsive to any increase or decrease in the parallelism degree, changing operating parameters of one or more of the processor, the memory and the nonvolatile memory array, by invoking one or more of a processor activation command, a memory activation command, and a nonvolatile memory command.

3. The method of claim 2 , further comprising:

responsive to issuance of the processor activation command, calculating a new hash function based on the new degree of parallelism; and

transitioning from a current hash function to the new hash function to control processor parallelism.

4. The method of claim 1 , wherein the power limit command includes the allowed power budget over the given time window.

5. The method of claim 1 , wherein the power consumption feedback represents measurements of power consumption of one or more of the processors, and the nonvolatile memory array.

6. The method of claim 1 , wherein the control circuit writes to registers of one or more of the processes, the memory and the nonvolatile memory devices.

7. The method of claim 1 , wherein receiving the power limit command further comprises:

determining if a power budget has changed by determining a difference between a current power budget and a new power budget specified in the power limit command.

8. The method of claim 7 , further comprising:

responsive to determining that the power budget has changed, invoking a power budget parallelism degree control loop that determines if the power budget has decreased;

responsive to the power budget decreasing, decreasing the parallelism degree; and

responsive to the power budget increasing, increasing the parallelism degree.

9. A method for adaptive power reduction for a solid-state storage device to dynamically control power consumption, the method comprising:

receiving a power limit command from a host, wherein receiving the power limit command further includes

determining if a power budget has changed by determining a difference between a current power budget and a new power budget specified in the power limit command;

receiving power consumption feedback;

using the power limit command and the power consumption feedback to calculate a new degree of parallelism, wherein calculating the new degree of parallelism further comprises:

responsive to determining that the power budget has not changed, then receiving the power consumption feedback;

invoking a power consumption stabilizer feedback control loop that determines if the current power consumption feedback is less than the current power budget;

responsive to determining that the current power consumption feedback is not less than the current power budget, then decreasing the parallelism degree; and

responsive to determining that the current power consumption feedback is less than the current power budget, then increasing the parallelism degree;

responsive to determining that the power budget has changed, invoking a power budget parallelism degree control loop that determines if the power budget has decreased;

responsive to the power budget decreasing, decreasing the parallelism degree; and

responsive to the power budget increasing, increasing the parallelism degree;

using the new degree of parallelism to control one or more of: i) processor parallelism, including activation of different numbers of processors, ii) memory parallelism, including memory pool length; and iii) nonvolatile memory parallelism, including activation of different numbers of nonvolatile memory devices.

10. A solid-state storage device, comprising:

a volatile memory;

a plurality of processors coupled to the volatile memory;

a nonvolatile memory array including a plurality of nonvolatile memory devices; and

a control circuit coupled to the volatile memory, the plurality of processors and the nonvolatile memory array, the control circuit configured to:

receive a power limit command from a host;

receive power consumption feedback;

use the power limit command and the power consumption feedback to calculate a new degree of parallelism within the solid-state storage device; and

use the new degree of parallelism for the solid-state storage device to control power consumption of the solid-state storage device to be within an allowed power budget over a given time window by controlling one or more of: i) processor parallelism, including activation of different numbers of processors within the solid-state storage device, ii) memory parallelism, including memory pool length for the solid-state storage device; and iii) nonvolatile memory parallelism, including activation of different numbers of the plurality of nonvolatile memory devices of the nonvolatile memory array within the solid-state storage device;

wherein the control circuit transmits a control signal to a voltage regulator to cause a voltage manager to output a different voltage to one or more of the processors, the memory and the nonvolatile memory devices; and

wherein the control circuit operates within the solid-state storage device, but external to the nonvolatile memory array.

11. The solid-state storage device of claim 10 , wherein the control circuit is further configured to:

responsive to any increase or decrease in the parallelism degree, change operating parameters of one or more of the processor, the memory and the nonvolatile memory array, by invoking one or more of a processor activation command, a memory activation command, and a nonvolatile memory command.

12. The solid-state storage device of claim 10 , wherein the control circuit is further configured to:

responsive to issuance of the processor activation command, calculate a new hash function based on the new degree of parallelism; and

transition from a current hash function to the new hash function to control processor parallelism.

13. The solid-state storage device of claim 10 , wherein the power consumption feedback represents measurements of power consumption of one or more of the processors, and the nonvolatile memory array.

14. The solid-state storage device of claim 10 , wherein the control circuit writes to registers of one or more of the processes, the memory and the nonvolatile memory devices.

15. The solid-state storage device of claim 10 , wherein the control circuit receives the power limit and determines if a power budget has changed by determining a difference between a current power budget and a new power budget specified in the power limit command.

16. The storage device of claim 15 , wherein:

responsive to determining that the power budget has changed, the control circuit invokes a power budget parallelism degree control loop that determines if the power budget has decreased;

responsive to the power budget decreasing, the control circuit decreases the parallelism degree; and

responsive to the power budget increasing, the control circuit increases the parallelism degree.

17. A storage device, comprising:

a volatile memory;

a plurality of processors coupled to the volatile memory;

a nonvolatile memory array; and

a control circuit coupled to the volatile memory, the plurality of processors and the nonvolatile memory array, the control circuit configured to:

receive a power limit command from a host and determine if a power budget has changed by determining a difference between a current power budget and a new power budget specified in the power limit command;

receive power consumption feedback;

use the power limit command and the power consumption feedback to calculate a new degree of parallelism wherein the new degree of parallelism is calculated by:

responsive to determining that the power budget has not changed, the control circuit receives the power consumption feedback;

the control circuit invokes a power consumption stabilizer feedback control loop that determines if the current power consumption feedback is less than the current power budget;

responsive to determining that the current power consumption feedback is not less than the current power budget, then the control circuit decreases the parallelism degree; and

responsive to determining that the current power consumption feedback is less than the current power budget, then the control circuit increases the parallelism degree; and

use the new degree of parallelism to control one or more of: i) processor parallelism, including activation of different numbers of processors, ii) memory parallelism, including memory pool length; and iii) nonvolatile memory parallelism, including activation of different numbers of nonvolatile memory devices; and wherein

responsive to determining that the power budget has changed, the control circuit invokes a power budget parallelism degree control loop that determines if the power budget has decreased;

responsive to the power budget decreasing, the control circuit decreases the parallelism degree; and

responsive to the power budget increasing, the control circuit increases the parallelism degree.

18. A method for adaptive power reduction for a solid-state storage device to dynamically control power consumption, the method comprising:

receiving a power limit command from a host at the solid-state storage device, the solid-state storage device including a plurality of processors, a memory and a plurality of nonvolatile memory devices;

receiving power consumption feedback;

using the power limit command and the power consumption feedback to calculate a new degree of parallelism for the solid-state storage device;

using the new degree of parallelism to control power consumption of the solid-state storage device to be within an allowed power budget over a given time window by controlling one or more of: i) processor parallelism, including activation of different numbers of processors within the solid-state storage device, ii) memory parallelism, including memory pool length for the memory of the solid-state storage device; and iii) nonvolatile memory parallelism, including activation of different numbers of nonvolatile memory devices within the solid-state storage device;

determining if a power budget has changed; and wherein calculating the new degree of parallelism further comprises

responsive to determining that the power budget has not changed, then receiving the power consumption feedback;

invoking a power consumption stabilizer feedback control loop that determines if the current power consumption feedback is less than the current power budget;

responsive to determining that the current power consumption feedback is not less than the current power budget, then decreasing the parallelism degree; and

responsive to determining that the current power consumption feedback is less than the current power budget, then increasing the parallelism degree.

19. A solid-state storage device, comprising:

a volatile memory;

a plurality of processors coupled to the volatile memory;

a nonvolatile memory array including a plurality of nonvolatile memory devices; and

a control circuit coupled to the volatile memory, the plurality of processors and the nonvolatile memory array, the control circuit configured to:

receive a power limit command from a host;

receive power consumption feedback;

use the power limit command and the power consumption feedback to calculate a new degree of parallelism within the solid-state storage device; and

use the new degree of parallelism for the solid-state storage device to control power consumption of the solid-state storage device to be within an allowed power budget over a given time window by controlling one or more of: i) processor parallelism, including activation of different numbers of processors within the solid-state storage device, ii) memory parallelism, including memory pool length for the solid-state storage device; and iii) nonvolatile memory parallelism, including activation of different numbers of the plurality of nonvolatile memory devices of the nonvolatile memory array within the solid-state storage device;

wherein control circuit is further configured to:

determine if a power budget has changed; and wherein the new degree of parallelism is calculated by

responsive to determining that the power budget has not changed, then receiving the power consumption feedback;

invoking a power consumption stabilizer feedback control loop that determines if the current power consumption feedback is less than the current power budget;

responsive to determining that the current power consumption feedback is not less than the current power budget, then decreasing the parallelism degree; and

responsive to determining that the current power consumption feedback is less than the current power budget, then increasing the parallelism degree.