Dynamic instrumentation based on detected errors

1. A method comprising:

identifying, by a processor, a sequence of memory related operations from an instruction stream, wherein the sequence comprises: a plurality of memory related operations that each reference a first address in memory, including a first memory related operation and a second memory related operation, wherein the second memory related operation is only able to execute subsequent to the first memory related operation;

responsive to detecting an error at the first memory related operation, instrumenting, by the processor, at least the second memory related operation based on the presence of the second memory related operation within the identified sequence.

2. The method of claim 1 , further comprising instrumenting, by the processor, the first memory related operation, wherein instrumenting the first memory related operation comprises:

instrumenting, by the processor, the first memory related operation with a branch out instruction to a portion of code capable of:

detecting an error at the first memory related operation;

responsive to detecting an error at the first memory related operation, causing additional instrumentation to be applied to at least the second memory related operation;

performing the first memory related operation; and

branching out to a subsequent instruction following the first memory related operation within the instruction stream.

3. The method of claim 1 , wherein each memory related operation is selected from the group consisting of: a load instruction and a store instruction.

4. The method of claim 1 , further comprising:

monitoring, by the processor, a state associated with the second memory related operation;

determining, by the processor, that the state associated with the second memory related operation indicates that the second memory related operation has been instrumented;

subsequent to detecting the error at the first memory related operation, detecting, by the processor, that the error is no longer present;

responsive to detecting that the error is no longer present, removing, by the processor, the instrumentation associated with at least the second memory related operation.

5. The method of claim 1 , wherein the sequence of memory related operations comprises a sequence of load instructions that load from a single definition, such that no path reaches the second memory related operation without first passing through the first memory related operation.

6. The method of claim 1 , wherein the sequence of memory related operations comprises a sequence of store instructions to a single address, wherein the second memory related operation may only occur after the first memory related operation.

7. The method of claim 1 , wherein the processor is a reduced instruction set computing (RISC) processor.

8. A computer program product comprising:

one or more computer readable storage media and program instructions stored on the one or more computer readable storage media, the program instructions comprising:

program instructions to identify, by a processor, a sequence of memory related operations from an instruction stream, wherein the sequence comprises: a plurality of memory related operations that each reference a first address in memory, including a first memory related operation and a second memory related operation, wherein the second memory related operation is only able to execute subsequent to the first memory related operation;

program instructions to, responsive to detecting an error at the first memory related operation, instrument, by the processor, at least the second memory related operation based on the presence of the second memory related operation within the identified sequence.

9. The computer program product of claim 8 , further comprising program instructions to instrument, by the processor, the first memory related operation, wherein program instructions to instrument the first memory related operation comprise:

program instructions to instrument, by the processor, the first memory related operation with a branch out instruction to a portion of code capable of:

detecting an error at the first memory related operation;

responsive to detecting an error at the first memory related operation, causing additional instrumentation to be applied to at least the second memory related operation;

performing the first memory related operation; and

branching out to a subsequent instruction following the first memory related operation within the instruction stream.

10. The computer program product of claim 8 , wherein each memory related operation is selected from the group consisting of a load instruction and a store instruction.

11. The computer program product of claim 8 , further comprising:

program instructions, stored on the one or more computer readable storage media, to monitor, by the processor, a state associated with the second memory related operation;

program instructions, stored on the one or more computer readable storage media, to determine, by the processor, that the state associated with the second memory related operation indicates that the second memory related operation has been instrumented;

program instructions, stored on the one or more computer readable storage media, to, subsequent to detecting the error at the first memory related operation, detect, by the processor, that the error is no longer present;

program instructions, stored on the one or more computer readable storage media, to, responsive to detecting that the error is no longer present, remove, by the processor, the instrumentation associated with at least the second memory related operation.

12. The computer program product of claim 8 , wherein the sequence of memory related operations comprises a sequence of load instructions that load from a single definition, such that no path reaches the second memory related operation without first passing through the first memory related operation.

13. The computer program product of claim 8 , wherein the sequence of memory related operations comprises a sequence of store instructions to a single address, wherein the second memory related operation may only occur after the first memory related operation.

14. The computer program product of claim 8 , wherein the processor is a reduced instruction set computing (RISC) processor.

15. A computer system for dynamically instrumenting a program at runtime, the computer system comprising:

one or more computer processors, one or more computer readable storage media, and program instructions stored on the computer readable storage media for execution by at least one of the one or more processors, the program instructions comprising:

program instructions to identify, by a processor, a sequence of memory related operations from an instruction stream, wherein the sequence comprises: a plurality of memory related operations that each reference a first address in memory, including a first memory related operation and a second memory related operation, wherein the second memory related operation is only able to execute subsequent to the first memory related operation;

program instructions to, responsive to detecting an error at the first memory related operation, instrument, by the processor, at least the second memory related operation based on the presence of the second memory related operation within the identified sequence.

16. The computer system of claim 15 , further comprising program instructions to instrument, by the processor, the first memory related operation, wherein program instructions to instrument the first memory related operation comprise:

program instructions to instrument, by the processor, the first memory related operation with a branch out instruction to a portion of code capable of:

detecting an error at the first memory related operation;

responsive to detecting an error at the first memory related operation, causing additional instrumentation to be applied to at least the second memory related operation;

performing the first memory related operation; and

branching out to a subsequent instruction following the first memory related operation within the instruction stream.

17. The computer system of claim 15 , wherein each memory related operation is selected from the group consisting of a load instruction and a store instruction.

18. The computer system of claim 15 , further comprising:

program instructions, stored on the computer readable storage media for execution by at least one of the one or more processors, to monitor, by the processor, a state associated with the second memory related operation;

program instructions, stored on the computer readable storage media for execution by at least one of the one or more processors, to determine, by the processor, that the state associated with the second memory related operation indicates that the second memory related operation has been instrumented;

program instructions, stored on the computer readable storage media for execution by at least one of the one or more processors, to, subsequent to detecting the error at the first memory related operation, detect, by the processor, that the error is no longer present;

program instructions, stored on the computer readable storage media for execution by at least one of the one or more processors, to, responsive to detecting that the error is no longer present, remove, by the processor, the instrumentation associated with at least the second memory related operation.

19. The computer system of claim 15 , wherein the sequence of memory related operations comprises a sequence of load instructions that load from a single definition, such that no path reaches the second memory related operation without first passing through the first memory related operation.

20. The computer system of claim 15 , wherein the sequence of memory related operations comprises a sequence of store instructions to a single address, wherein the second memory related operation may only occur after the first memory related operation.