Semiconductor device having a multi-terminal transistor layout
A semiconductor device includes a gate region, a source/drain region and an insulating layer between the gate region and the source/drain region. The source/drain region includes a first leg extending in a first direction, a second leg extending in parallel with the first leg, and a third leg connected between the first leg and the second leg.
1. A semiconductor device, comprising:
a gate region;
a source/drain region; and
an insulating layer between the gate region and the source/drain region;
wherein the source/drain region includes a first leg extending in a first direction, a second leg separate from and extending in parallel with the first leg, and a third leg arranged to connect the first leg to the second leg separate from the first leg; one end of the third leg is in contact with a portion between two ends of the first leg; the gate region and each of the first leg, the second leg and the third leg are disposed one over the other, one of the gate region and the third leg is disposed directly over the other of the gate region and the third leg along a direction in which the one of the gate region and the third leg is orthogonally projected onto the other of the gate region and the third leg, and the gate region is common to the first leg, the second leg and the third leg of the source/drain region.
2. The semiconductor device according to claim 1 , wherein the third leg extends in a second direction different from the first direction.
3. The semiconductor device according to claim 2 , wherein the second direction is orthogonal to the first direction.
4. The semiconductor device according to claim 1 , wherein the source/drain region includes a first source/drain terminal, a second source/drain terminal and a third source/drain terminal, which are not overlapped with the gate region.
5. The semiconductor device according to claim 4 , wherein the first source/drain terminal and the gate region define a first transistor, the second source/drain terminal and the gate region define a second transistor, and the third source/drain terminal and the gate region define a third transistor.
6. The semiconductor device according to claim 1 , wherein another end of the third leg is connected to one end of the second leg.
7. The semiconductor device according to claim 4 , further comprising a fourth source/drain terminal.
8. The semiconductor device according to claim 7 , wherein the fourth source/drain terminal and the gate region define a fourth transistor.
9. The semiconductor device according to claim 1 , wherein the third leg is disposed proximate to source/drain terminals on the first leg and the second leg that define a charging current path together with the third leg.
10. The semiconductor device according to claim 9 , wherein the third leg has a shape of a hump.
11. A semiconductor device, comprising:
a gate region; and
a source/drain region, comprising:
a first source/drain terminal;
a second source/drain terminal; and
a third source/drain terminal,
wherein the first, second and third source/drain terminals are separate from each other and each of the first, second and third source/drain terminals is not overlapped with the gate region; the source/drain region further comprises a first leg, a second leg and a third leg, and the second leg separates from and extends in parallel with the first leg; the third leg is arranged to connect the first leg to the second leg separate from the first leg, and one end of the third leg is in contact with a portion between different ends of the first leg; the first source/drain terminal and the second source/drain terminal are connected to the different ends of the first leg respectively, and the third source/drain terminal is connected to one end of the second leg; the gate region and each of the first leg, the second leg and the third leg are disposed one over the other, one of the gate region and the third leg is disposed directly over the other of the gate region and the third leg along a direction in which the one of the gate region and the third leg is orthogonally projected onto the other of the gate region and the third leg, and the gate region is common to the first leg, the second leg and the third leg of the source/drain region.
12. The semiconductor device according to claim 11 , wherein the first source/drain terminal and the gate region define a first transistor, the second source/drain terminal and the gate region define a second transistor, and the third source/drain terminal and the gate region define a third transistor.
13. The semiconductor device according to claim 11 , wherein the first leg extends in a first direction from the first source/drain terminal to the second source/drain terminal.
14. The semiconductor device according to claim 11 , wherein another end of the third leg is in contact with a portion between different ends of the second leg.
15. The semiconductor device according to claim 11 , wherein another end of the third leg is connected to one end of the second leg.
16. The semiconductor device according to claim 11 , further comprising a fourth source/drain terminal not overlapped with the gate region.
17. The semiconductor device according to claim 16 , wherein the second leg extending from the third source/drain terminal to the fourth source/drain terminal.
18. The semiconductor device according to claim 16 , wherein the fourth source/drain terminal and the gate region define a fourth transistor.
19. The semiconductor device according to claim 11 , wherein the source/drain region is disposed between the gate region and a substrate of the semiconductor device.
20. The semiconductor device according to claim 11 , wherein the gate region is disposed between the source/drain region and a substrate of the semiconductor device.