Electromechanical power switch integrated circuits and devices and methods thereof
An electromechanical power switch device and methods thereof. At least some of the illustrative embodiments are devices including a semiconductor substrate, at least one integrated circuit device on a front surface of the semiconductor substrate, an insulating layer on the at least one integrated circuit device, and an electromechanical power switch on the insulating layer. By way of example, the electromechanical power switch may include a source and a drain, a body region disposed between the source and the drain, and a gate including a switching metal layer. In some embodiments, the body region includes a first body portion and a second body portion spaced a distance from the first body portion and defining a body discontinuity therebetween. Additionally, in various examples, the switching metal layer may be disposed over the body discontinuity.
1. A semiconductor device comprising:
a semiconductor substrate including at least one integrated circuit device on a front surface of the semiconductor substrate;
an insulating layer on the front surface including over the at least one integrated circuit device;
an electromechanical power switch on the insulating layer, wherein the electromechanical power switch includes a source and a drain, a body region disposed between the source and the drain, and a gate including a switching metal layer; and
a first decoupling capacitor formed over at least one of the source and the drain.
2. The semiconductor device of claim 1 , wherein the first decoupling capacitor includes a 3D capacitor having a plurality of 3D features.
3. The semiconductor device of claim 2 , wherein the plurality of 3D features include at least one of fins, ridges, valleys, or mesas.
4. The semiconductor device of claim 2 , wherein the plurality of 3D features include 3D metal features, and wherein the first decoupling capacitor further includes a dielectric layer formed over the 3D metal features and an electrode formed over the dielectric layer.
5. The semiconductor device of claim 1 , wherein the first decoupling capacitor includes a 3D multi-layer capacitor, and wherein the 3D multi-layer capacitor comprises:
a trench portion;
a first metal region on the insulating layer and adjacent to a first side of the trench portion;
a second metal region on the insulating layer and adjacent to a second side of the trench portion opposite the first side of the trench portion;
a pair of interdigitated metal electrodes disposed within the trench portion, wherein a first electrode of the pair of interdigitated metal electrodes contacts the first metal region, and wherein a second electrode of the pair of interdigitated metal electrodes contacts the second metal region;
and
a plurality of dielectric layers disposed within the trench portion and between neighboring electrodes of the pair of interdigitated metal electrodes.
6. The semiconductor device of claim 5 , wherein the trench portion extends into the insulating layer.
7. The semiconductor device of claim 1 , wherein the body region includes a first body portion and a second body portion spaced a distance from the first body portion and defining a body discontinuity therebetween, and wherein the switching metal layer is disposed over the body discontinuity.
8. The semiconductor device of claim 1 , further comprising:
a second decoupling capacitor formed over the other of the at least one of the source and the drain, wherein the second decoupling capacitor includes a 3D capacitor having a plurality of 3D features.
9. A semiconductor device comprising:
a semiconductor substrate including at least one integrated circuit device on a front surface of the semiconductor substrate;
an insulating layer on the front surface including over the at least one integrated circuit device;
an electromechanical power switch on the insulating layer, wherein the electromechanical power switch includes a source and a drain, a body region disposed between the source and the drain, and a gate including a switching metal layer; and
a first 3D capacitor formed over at least one of the source and the drain.
10. The semiconductor device of claim 9 , further comprising:
a second 3D capacitor formed over the other of the at least one of the source and the drain.
11. The semiconductor device of claim 10 , wherein at least one of the first 3D capacitor and the second 3D capacitor includes fins, ridges, valleys, or mesas.
12. The semiconductor device of claim 10 , wherein at least one of the first 3D capacitor and the second 3D capacitor includes a 3D multi-layer capacitor, and wherein the 3D multi-layer capacitor comprises:
a trench portion;
a first metal region on the insulating layer and adjacent to a first side of the trench portion;
a second metal region on the insulating layer and adjacent to a second side of the trench portion opposite the first side of the trench portion;
a pair of interdigitated metal electrodes disposed within the trench portion, wherein a first electrode of the pair of interdigitated metal electrodes contacts the first metal region, and wherein a second electrode of the pair of interdigitated metal electrodes contacts the second metal region;
and
a plurality of dielectric layers disposed within the trench portion and between neighboring electrodes of the pair of interdigitated metal electrodes.
13. A semiconductor device comprising:
a semiconductor substrate including at least one integrated circuit device on a front surface of the semiconductor substrate;
an insulating layer on the front surface including over the at least one integrated circuit device;
an electromechanical power switch on the insulating layer, wherein the electromechanical power switch includes a source and a drain, a body region disposed between the source and the drain, and a gate including a switching metal layer; and
a 3D multi-layer decoupling capacitor, the 3D multi-layer decoupling capacitor comprising:
a trench portion;
a first metal region on the insulating layer and adjacent to a first side of the trench portion;
a second metal region on the insulating layer and adjacent to a second side of the trench portion opposite the first side of the trench portion;
a pair of interdigitated metal electrodes disposed within the trench portion, wherein a first electrode of the pair of interdigitated metal electrodes contacts the first metal region, and wherein a second electrode of the pair of interdigitated metal electrodes contacts the second metal region;
and
a plurality of dielectric layers disposed within the trench portion and between neighboring electrodes of the pair of interdigitated metal electrodes.
14. The semiconductor device of claim 13 , wherein the trench portion extends into the insulating layer.
15. The semiconductor device of claim 13 , wherein the first electrode of the pair of interdigitated metal electrodes includes at least two first metal lines.
16. The semiconductor device of claim 15 , wherein the at least two first metal lines are interposed by a portion of the second electrode.
17. The semiconductor device of claim 13 , wherein the second electrode of the pair of interdigitated metal electrodes includes at least two second metal lines.
18. The semiconductor device of claim 17 , wherein the at least two second metal lines are interposed by a portion of the first electrode.
19. The semiconductor device of claim 13 , wherein the first electrode of the pair of interdigitated metal electrodes includes a first plurality of metal lines, wherein the first plurality of metal lines contact each other over the first metal region, and wherein one of the first plurality of metal lines directly contacts the first metal region.
20. The semiconductor device of claim 13 , wherein the second electrode of the pair of interdigitated metal electrodes includes a second plurality of metal lines, wherein the second plurality of metal lines contact each other over the second metal region, and wherein one of the second plurality of metal lines directly contacts the second metal region.