Vertical vacuum channel transistor with minimized air gap between tip and gate
A method is presented for controlling an electric field from a gate structure. The method includes forming a hardmask over a fin stack including a plurality of layers, forming a first dielectric layer over the hardmask, forming a sacrificial layer over the first dielectric layer, etching the sacrificial layer to expose a top surface of the first dielectric layer, depositing a second dielectric layer in direct contact with exposed surfaces of the first dielectric layer and the sacrificial layer, removing a layer of the plurality of layers of the fin stack to define an air gap within the fin stack, and forming triangle-shaped epitaxial growths within the air gap defined within the fin stack.
1. A semiconductor structure for controlling an electric field from a gate structure, the semiconductor structure comprising:
a fin stack including a plurality of layers disposed between inner surfaces of a first dielectric layer;
a conductive material disposed in direct contact with outer surfaces of the first dielectric layer; and
an air gap defined within the fin stack with epitaxial growths disposed therein.
2. The semiconductor structure of claim 1 , wherein a second dielectric layer directly contacts outer surfaces of the conductive material.
3. The semiconductor structure of claim 1 , wherein a portion of the first dielectric layer is formed in direct contact with spacers.
4. The semiconductor structure of claim 1 , wherein the epitaxial growths are triangle-shaped epitaxial growths created in a tip-to-tip configuration.
5. The semiconductor structure of claim 1 , wherein a nitride-based dielectric is disposed over the conductive material.
6. The semiconductor structure of claim 1 , wherein gate, emitter, and collector contacts are formed.
7. The semiconductor structure of claim 1 , wherein the epitaxial growths directly contact the fin stacks.
8. The semiconductor structure of claim 1 , wherein the epitaxial growths minimize a space defined by the air gap.
9. The semiconductor structure of claim 8 , wherein minimizing the space defined by the air gap allows for the controlling of the electric field from the gate structure of a transistor.
10. The semiconductor structure of claim 1 , wherein the epitaxial growths are formed from silicon germanium (SiGe).
11. The semiconductor structure of claim 1 , wherein the epitaxial growths are prevented from contacting each other within the air gap.
12. A semiconductor structure, comprising:
a fin stack including a plurality of layers disposed between inner surfaces of a first dielectric layer;
a conductive material disposed in direct contact with outer surfaces of the first dielectric layer; and
an air gap defined within the fin stack, the air gap accommodating triangle-shaped epitaxial growths created in a tip-to-tip configuration.
13. The semiconductor structure of claim 12 , wherein a second dielectric layer directly contacts outer surfaces of the conductive material.
14. The semiconductor structure of claim 12 , wherein a portion of the first dielectric layer is formed in direct contact with spacers.
15. The semiconductor structure of claim 12 , wherein a nitride-based dielectric is disposed over the conductive material.
16. The semiconductor structure of claim 12 , wherein gate, emitter, and collector contacts are formed.
17. The semiconductor structure of claim 12 , wherein the triangle-shaped epitaxial growths directly contact the fin stacks.
18. The semiconductor structure of claim 12 , wherein the triangle-shaped epitaxial growths minimize a space defined by the air gap.
19. The semiconductor structure of claim 18 , wherein minimizing the space defined by the air gap allows for the controlling of the electric field from the gate structure of a transistor.
20. The semiconductor structure of claim 12 , wherein the triangle-shaped epitaxial growths are formed from silicon germanium (SiGe).