Directed self-assembly for copper patterning
A process for forming patterned copper lines, a pattern of copper lines, and an electronic device having patterned copper lines and at least one CMOS circuit. The process includes assembling an etch stack, wherein the etch stack includes a resist and a copper substrate. The process also includes lithographically patterning the resist to produce a template, and forming a patterned block copolymer mask layer by directed self-assembly. Additionally, the process includes etching portions of the block copolymer mask layer to produce a patterned block copolymer mask layer, and transferring a pattern formed by the template and the patterned block copolymer mask layer to the copper substrate to form the patterned copper lines.
1. A process of forming patterned copper lines, comprising:
assembling an etch stack, wherein the etch stack includes a resist, a hardmask, an organic planarizing layer (OPL), and a copper substrate, and wherein the copper substrate has been annealed at a temperature above 200° C.;
lithographically patterning the resist to produce a template;
forming a patterned block copolymer mask layer on the etch stack by directed self-assembly, wherein the patterned block copolymer includes a first block and a second block;
etching portions of the block copolymer mask layer, wherein the etching removes the first block to produce a first pattern;
etching the first pattern into the hardmask;
partially removing the second block;
etching the first pattern into the OPL, wherein the etching the first pattern includes removing the remainder of the second block and partially removing the patterned hardmask;
coating the patterned OPL with a coating material;
etching back a layer of the coating material and the remainder of the hardmask to expose the surface of the patterned OPL;
removing the patterned OPL to produce a second pattern; and
transferring the second pattern to the copper substrate to form the patterned copper lines, wherein the patterned copper lines have a pitch that is less than 30 nm.
2. The process of claim 1 , wherein the etch stack also includes a dielectric layer, a liner layer, and a barrier layer.
3. The process of claim 1 , wherein the organic planarizing layer is amorphous carbon.
4. The process of claim 1 , wherein the etching the first pattern into the hardmask includes at least one reactive ion etching step.
5. The process of claim 1 , wherein the etching the first pattern into the OPL includes at least one plasma-based etching step.
6. The process of claim 5 , wherein the plasma-based etching step uses an O 2 -based plasma.
7. The process of claim 1 , wherein the hardmask is made of a material selected from a group consisting of silicon, silicon nitride, silicon oxide, titanium nitride, titanium oxides, titanium oxynitrides, tantalum nitride, hafnium oxides, niobium nitride, lanthanum oxide, silicon oxynitrides, zirconium oxides, and tin oxides.
8. The process of claim 1 , wherein the block copolymer mask layer is a lamellae-forming block copolymer.
9. The process of claim 1 , wherein the block copolymer is selected from a group consisting of poly(styrene)-poly(methyl methacrylate), poly(styrene)-b-poly(methyl methacrylate), poly(ethylene oxide)-poly(lactic acid), and a high chi block copolymer.
10. The process of claim 1 , further comprising integrating the patterned copper lines with at least one complementary metal-oxide-semiconductor circuit.