3D semiconductor device and structure
A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a second metal layer overlaying, at least in part the third transistors; Input/Output pads to provide connection to external devices, a local power grid to distribute power to the plurality of logic gates, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes an Serializer/Deserializer (“SerDes”) structure connected to at least one of the Input/Output pads, where a memory cell includes at least one of the third transistors.
1. A 3D semiconductor device, the device comprising:
a first single crystal layer comprising a plurality of first transistors and a first metal layer,
wherein said first metal layer comprises interconnecting said first transistors forming, at least in part a plurality of logic gates;
a plurality of second transistors atop, at least in part said first single crystal layer;
a plurality of third transistors overlaying, at least in part said second transistors;
a second metal layer above, at least in part said third transistors;
Input/Output pads to provide connection to external devices;
a global power grid to distribute power to said device, said global power grid overlaying, at least in part said first metal layer; and
a local power grid to distribute power to said plurality of logic gates,
wherein said third transistors are aligned to said first transistors with less than 40 nm misalignment,
wherein said first single crystal layer comprises an Serializer/Deserializer (“SerDes”) structure connected to at least one of said Input/Output pads,
wherein said global power grid is connected to said local power grid by a plurality of vias,
wherein at least one of said plurality of vias has a radius of less than 200 nm,
wherein at least one of said third transistors comprises a source, a drain, and a transistor channel,
wherein said source, said drain and said transistor channel comprise a same dopant type,
wherein at least one of said third transistors is at least partially atop at least one of said first transistors, and
wherein a memory cell comprises at least one of said third transistors.
2. The 3D semiconductor device according to claim 1 ,
wherein one of said second transistors is self-aligned to at least one of said third transistors, and
wherein said self-aligned comprises meaning said second transistor and said third transistor were processed using at least one common lithography step.
3. The 3D semiconductor device according to claim 1 , further comprising:
a connective path from said second transistors to said first transistors,
wherein said path comprises a through-layer via,
wherein said through-layer via comprises a material whose co-efficient of thermal expansion is within 50 percent of a coefficient of thermal expansion of said first single crystal layer.
4. The 3D semiconductor device according to claim 1 ,
wherein said second transistors comprise polysilicon.
5. The 3D semiconductor device according to claim 1 , further comprising:
a Phase Lock Loop structure,
wherein said SerDes is connected to said Phase Lock Loop structure.
6. The 3D semiconductor device according to claim 1 ,
wherein said memory is a NAND non-volatile memory.
7. The 3D semiconductor device according to claim 1 ,
wherein said global power grid comprises a first conductor and said local power grid comprises a second conductor, and
wherein said first conductor has an at least 2 times larger current carrying capacity than said second conductor.
8. A 3D semiconductor device, the device comprising:
a first single crystal layer comprising a plurality of first transistors and a first metal layer,
wherein said first metal layer comprises interconnecting said first transistors forming, at least in part a plurality of logic gates;
a plurality of second transistors atop, at least in part said first single crystal layer;
a plurality of third transistors overlaying, at least in part said second transistors;
a second metal layer above, at least in part said third transistors; and
Input/Output pads to provide connection to external devices,
wherein said third transistors are aligned to said first transistors with less than 40 nm misalignment,
wherein said first single crystal layer comprises an SerDes structure connected to at least one of said Input/Output pads,
wherein at least one of said third transistors comprises a source, a drain, and a transistor channel,
wherein said source, said drain and said transistor channel comprise a same dopant type, and
wherein a memory cell comprises at least one of said third transistors.
9. The 3D semiconductor device according to claim 8 ,
wherein one of said second transistors is self-aligned to at least one of said third transistors, and
wherein said self-aligned comprises meaning said second transistor and said third transistor were processed using at least one common lithography step.
10. The 3D semiconductor device according to claim 8 , further comprising:
a connective path from said second transistors to said first transistors,
wherein said path comprises a through-layer via,
wherein said through-layer via comprises a material whose co-efficient of thermal expansion is within 50 percent of a coefficient of thermal expansion of said first single crystal layer.
11. The 3D semiconductor device according to claim 8 ,
wherein said second transistors comprise polysilicon.
12. The 3D semiconductor device according to claim 8 ,
wherein said memory is a NAND non-volatile memory.
13. The 3D semiconductor device according to claim 8 ,
wherein at least one of said third transistors at least partially overlays at least one of said first transistors.
14. The 3D semiconductor device according to claim 8 , further comprising:
a first set of external connections under said first single crystal layer to connect said device to a first external device; and
a second set of external connections above said second metal layer to connect said device to a second external device,
wherein said first set of external connections comprises a through silicon via (TSV).
15. A 3D semiconductor device, the device comprising:
a first single crystal layer comprising a plurality of first transistors and a first metal layer,
wherein said first metal layer comprises interconnecting said first transistors forming, at least in part a plurality of logic gates;
a plurality of second transistors atop, at least in part said first single crystal layer;
a plurality of third transistors overlaying, at least in part said second transistors;
a second metal layer above, at least in part said third transistors; and
Input/Output pads to provide connection to external devices,
wherein said third transistors are aligned with less than 40 nm misalignment to said first transistors, and
wherein said first single crystal layer comprises an Electrostatic Discharge (“ESD”) structure connected to at least one of said Input/Output pads.
16. The 3D semiconductor device according to claim 15 ,
wherein said third transistors comprise polysilicon.
17. The 3D semiconductor device according to claim 15 ,
wherein at least one of said third transistors comprises a source, a drain, and a transistor channel,
wherein said source, said drain and said transistor channel comprise the same dopant type.
18. The 3D semiconductor device according to claim 15 ,
wherein one of said second transistors is self-aligned to at least one of said third transistors, and
wherein said self-aligned comprises meaning said second transistor and said third transistor were processed using at least one common lithography step.
19. The 3D semiconductor device according to claim 15 ,
wherein a memory cell comprises at least one of said third transistors, and
wherein said memory cell is at least partially atop at least one of said logic gates.
20. The 3D semiconductor device according to claim 15 , further comprising:
a connective path from said second transistors to said first transistors,
wherein said path comprises a through-layer via,
wherein said through-layer via comprises a material whose co-efficient of thermal expansion is within 50 percent of a coefficient of thermal expansion of said first single crystal layer.