IP Library Granted Patent US 10,600,684
Granted Patent B2
US 10,600,684 · App. 16/224,337 · Granted Mar 24, 2020

Ultra-thin diffusion barriers

Inventors: Susmit Singha Roy (Mountain View, CA); Yihong Chen (San Jose, CA); Abhijit Basu Mallick (Fremont, CA); Srinivas Gandikota (Santa Clara, CA)
Assignee: APPLIED MATERIALS, INC.
H01L21/76852H01L21/0217H01L21/0228H01L21/0234H01L21/02178H01L21/02211H01L21/02274H01L21/02315H01L21/31053H01L21/324H01L21/76864
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Quick Facts
Patent No.
US 10,600,684
App. No.
16/224,337
Granted
Mar 24, 2020
Kind
B2
Abstract

In one embodiment, a method of forming a barrier layer is provided. The method includes positioning a substrate in a processing chamber, forming a barrier layer over the substrate and in contact with the underlayer, and annealing the substrate. The substrate comprises at least one underlayer having cobalt, tungsten, or copper. The barrier layer has a thickness of less than 70 angstroms.

Claims (29)

1. A method of forming a semiconductor device, comprising:

positioning a device intermediate in a processing chamber, the device intermediate comprising:

a silicon substrate;

a dielectric layer disposed on the silicon substrate; and

conductive features in contact with the silicon substrate and extending through openings in the dielectric layer;

forming a barrier layer over the device intermediate;

depositing a gap fill material on the barrier layer, wherein the gap fill material is a flowable dielectric material;

removing a portion of the gap fill material to planarize an upper surface of the gap fill material; and

annealing the device intermediate at a temperature of about 400° C. to about 500° C. and a pressure of about 10 torr to about 700 torr.

2. The method of claim 1 , wherein the barrier layer has a thickness of less than 30 angstroms.

3. The method of claim 1 , wherein the barrier layer comprises amorphous silicon deposited by plasma enhanced chemical vapor deposition.

4. The method of claim 1 , wherein the barrier layer comprises amorphous silicon nitride deposited by plasma enhanced chemical vapor deposition.

5. The method of claim 1 , wherein the barrier layer comprises aluminum oxide deposited by atomic layer deposition.

6. The method of claim 1 , wherein the gap fill material is planarized by chemical mechanical polishing.

7. The method of claim 1 , wherein the barrier layer comprises silicon nitride deposited by plasma enhanced chemical vapor deposition.

8. The method of claim 7 , wherein the deposition of the silicon nitride comprises a mid-treatment soak.

9. The method of claim 8 , wherein the barrier layer is formed of two or more portions.

10. A method of forming a semiconductor device, comprising:

positioning a device intermediate in a processing chamber, the device intermediate comprising:

a silicon substrate;

at least one dielectric layer disposed on the silicon substrate; and

conductive features in contact with the silicon substrate and extending through openings in the dielectric layer;

forming a barrier layer over the device intermediate, the barrier layer having a thickness of no more than 70 angstroms;

depositing a gap fill material on the barrier layer, wherein the gap fill material is a flowable dielectric material;

removing a portion of the gap fill material to planarize an upper surface of the device intermediate; and

annealing the device intermediate.

11. The method of claim 10 , wherein the barrier layer comprises silicon nitride deposited by plasma enhanced chemical vapor deposition.

12. The method of claim 10 , wherein the barrier layer comprises amorphous silicon deposited by plasma enhanced chemical vapor deposition.

13. The method of claim 10 , wherein the barrier layer comprises amorphous silicon nitride deposited by plasma enhanced chemical vapor deposition.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 19, 2018
From: ROY, SUSMIT SINGHA; CHEN, YIHONG; MALLICK, ABHIJIT BASU; GANDIKOTA, SRINIVAS
To: APPLIED MATERIALS, INC.
Reel/Frame 047814/0620 →
Continuity (2)
Provisional Application 62607455 · Dec 19, 2017
Related Publication 20190189506A1 · Jun 20, 2019