Strained silicon germanium fin with block source/drain epitaxy and improved overlay capacitance

1. A semiconductor structure comprising:

a functional gate structure straddling over a first portion of at least one strained silicon germanium alloy fin;

a source region located on a source-side of the functional gate structure and comprising, a first end portion of the at least one strained silicon germanium alloy fin, and a source-side silicon pedestal structure located on opposing sidewalls of the first end portion of the at least one strained silicon germanium alloy fin;

a drain region located on a drain-side of the functional gate structure and comprising, a second end portion of the at least one strained silicon germanium alloy fin, and a drain-side silicon pedestal structure located on opposing sidewalls of the second end portion of the at least one strained silicon germanium alloy fin;

a first raised source/drain (S/D) structure present on the source-side silicon pedestal structure, wherein the first raised silicon raised source/drain (S/D) structure has a sidewall surface that overhangs a sidewall surface of the source-side silicon pedestal structure;

a second raised source/drain (S/D) structure present on the drain-side silicon pedestal structure, wherein the second raised silicon raised source/drain (S/D) structure has a sidewall surface that overhangs a sidewall surface of the drain-side silicon pedestal structure;

a source-side gate spacer located on a first sidewall of the functional gate structure, wherein the source-side gate spacer has a first region that is located on the at least one strained silicon germanium alloy fin, and a second region that is present laterally adjacent the at least one strained silicon germanium alloy fin that has an upper portion and a lower portion, the lower portion of the source-side gate spacer fills an undercut region beneath the overhang present in the source-side;

a drain-side gate spacer located on a second sidewall of the functional gate structure, wherein the drain-side gate spacer has a first region that is located on the at least one strained silicon germanium alloy fin, and a second region that is present laterally adjacent the at least one strained silicon germanium alloy fin that has an upper portion and a lower portion, the lower portion of the drain-side gate spacer fills an undercut region beneath the overhang present in the drain-side;

a source-side dielectric spacer located between the upper portion of the source-side gate spacer and the first raised source/drain structures, wherein a sidewall surface of the source-side dielectric spacer directly contacts the sidewall surface of the first raised source/drain structure; and

a drain-side dielectric spacer located between the upper portion of the drain-side gate spacer and the second raised source/drain structures, wherein a sidewall surface of the drain-side dielectric spacer directly contacts the sidewall surface of the second raised source/drain structure.

2. The semiconductor structure of claim 1 , further comprising an interlevel dielectric layer located on the first and second raised source/drain (S/D) structures, the interlevel dielectric layer having a first overhanging portion located above the source-side silicon pedestal structure and a second overhanging portion located above the drain-side silicon pedestal structure.

3. The semiconductor structure of claim 2 , wherein the upper portion of the source-side and drain-side gate spacers and the source-side and drain-side dielectric spacers extend to a topmost surface of the interlevel dielectric layer.

4. The semiconductor structure of claim 1 , wherein the strained silicon germanium alloy fin has a height that is less than a height of each of the silicon pedestal structures.

5. The semiconductor structure of claim 1 , wherein the first region of both the source-side and drain-side gate spacers, the upper portion of the second region of both the source-side gate spacer and the drain-side gate spacer and the lower portion of second region of both the source-side gate spacer and the drain-side gate spacer have a same thickness.

6. The semiconductor structure of claim 1 , wherein the first region of both of the source-side gate spacer and the drain-side gate spacer has a first thickness, the upper portion of the second region of both of the source-side gate spacer and the drain-side gate spacer has the first thickness and the lower portion of the second region of both of the source-side gate spacer and the drain-side gate spacer has a second thickness, wherein the second thickness is greater than the first thickness.

7. The semiconductor structure of claim 1 , wherein the at least one strained silicon germanium alloy fin is present on a surface of a doped semiconductor region of a substrate.

8. The semiconductor structure of claim 1 , wherein the functional gate structure comprises a gate dielectric portion and a gate conductor portion.

9. The semiconductor structure of claim 8 , wherein the gate dielectric portion has a topmost surface that is coplanar with a topmost surface of each of the gate conductor portion, the source-side dielectric spacer, the drain-side dielectric spacer, the source-side gate spacer, and the drain-side gate spacer.

10. The semiconductor structure of claim 8 , wherein the gate conductor portion has an upper portion of a first width, and a lower portion of a second width that is greater than the first width.

11. The semiconductor structure of claim 1 , wherein the source-side dielectric spacer has a bottommost surface that is coplanar with a bottommost surface of the first raised source/drain (S/D) structure, and the drain-side dielectric spacer has a bottommost surface that is coplanar with a bottommost surface of the second raised source/drain (S/D) structure.

12. The semiconductor structure of claim 1 , wherein the at least one strained silicon germanium alloy fin has a germanium content of from 20 atomic percent to 60 atomic percent.

13. The semiconductor structure of claim 1 , wherein both the source-side gate spacer and the drain-side gate spacer are composed of a dielectric material that includes atoms of Si, O, C and H.

14. The semiconductor structure of claim 13 , wherein the dielectric material that provides the source-side gate and the drain-side gate spacer further comprises N.

15. The semiconductor structure of claim 1 , wherein the sidewall surface of the first raised source/drain (S/D) structure overhangs the sidewall surface of the source-side silicon pedestal structure by a width from 2 nm to 20 nm, and wherein the sidewall surface of the second raised source/drain structure overhangs the sidewall surface of the drain-side silicon pedestal structure by a width from 2 nm to 20 nm.

16. The semiconductor structure of claim 1 , wherein a topmost surface of each of the source-side gate spacer and the drain-side gate spacer is coplanar with a topmost surface of each of the source-side dielectric spacer and the drain-side dielectric spacer.

17. The semiconductor structure of claim 1 , wherein a bottommost surface of the source-side dielectric spacer directly contacts a surface of the source-side gate spacer, and wherein a bottommost surface of the drain-side dielectric spacer directly contacts a surface of the drain-side gate spacer.

18. The semiconductor structure of claim 17 , wherein the bottommost surface of the source-side dielectric spacer is coplanar with a bottommost surface of first raised source/drain (S/D) structure, and the bottommost surface of the drain-side dielectric spacer is coplanar with a bottommost surface of second raised source/drain (S/D) structure.