Identifying lane errors using a pseudo-random binary sequence

1. A device comprising:

a first die comprising a pseudo-random binary sequence (“PRBS”) generator that outputs test signals on parallel lanes, the test signals comprising n bits of a PRBS generated by the PRBS generator and output in parallel, one bit per lane, where n is a power of two; and

a second die comprising a PRBS checker that compares at least a portion of the test signals with reference signals to identify a particular lane associated with an error.

2. A device comprising:

a first die comprising a pseudo-random binary sequence (“PRBS”) generator that outputs test signals on parallel lanes; and

a second die comprising:

a PRBS checker that compares at least a portion of the test signals with reference signals to identify a particular lane associated with an error; and

a decimator that outputs an n-bit word to the PRBS checker, the n-bit word formed by selecting every nth bit of a PRBS generated by the PRBS generator as one bit of the n-bit word, a first-selected bit of the n-bit word determined based on a lane to be checked, where n is a power of two.

3. The device of claim 1 , wherein the second die comprises a decimator comprising a multiplexer, coupled to the parallel lanes, that outputs n bits sequentially received on any one selected lane.

4. The device of claim 3 , wherein the decimator comprises a serial-to-parallel converter, coupled to the multiplexer and the PRBS checker, that receives n serial bits from the multiplexer and output the n bits in parallel to the PRBS checker.

5. The device of claim 1 , wherein the reference signals comprise a PRBS generated by the PRBS checker separately from the PRBS generator.

6. The device of claim 5 , wherein the same PRBS generated by the PRBS checker is used to check each lane for errors.

7. A method comprising:

generating test signals comprising at least a portion of a pseudo-random binary sequence (“PRBS”);

transmitting the test signals on parallel lanes, the test signals comprising n bits of the PRBS being transmitted in parallel, one bit per lane, where n is a power of two;

comparing at least a portion of the test signals with reference signals; and

identifying a particular lane associated with an error based on the comparison.

8. A method comprising:

generating test signals comprising at least a portion of a pseudo-random binary sequence (“PRBS”);

transmitting the test signals on parallel lanes;

decimating the test signals to obtain a decimated portion of the test signals;

comparing the decimated portion of the test signals with reference signals; and

identifying a particular lane associated with an error based on the comparison.

9. The method of claim 8 , wherein decimating the test signals comprises forming an n-bit word as one bit of the n-bit word, a first-selected bit of the n-bit word determined based on a lane to be checked, where n is a power of two.

10. The method of claim 9 , wherein comparing the test signals with the reference signals comprises comparing the n-bit word with a PRBS generated separately from the test signals.

11. The method of claim 7 , wherein the reference signals comprise a PRBS generated separately from the test signals.

12. The method of claim 11 , wherein comparing the test signals with the reference signals comprises comparing the separately-generated PRBS with one n-bit word per lane.

13. A 2.5-dimensional integrated circuit comprising:

a first die comprising a pseudo-random binary sequence (“PRBS”) generator that outputs test signals on parallel lanes, the test signals comprising n bits of a PRBS generated by the PRBS generator and output in parallel, one bit per lane, where n is a power of two;

a second die comprising a PRBS checker that compares at least a portion of the test signals with reference signals to identify a particular lane associated with an error; and

an interposer, that couples to a printed circuit board, coupled to the first and second dies, the interposer comprising the parallel lanes.

14. The integrated circuit of claim 13 , wherein the second die comprises a decimator that outputs an n-bit word to the PRBS checker, the n-bit word formed by selecting every nth bit of a PRBS generated by the PRBS generator as one bit of the n-bit word, a first-selected bit of the n-bit word determined based on a lane to be checked.

15. The integrated circuit of claim 13 , wherein the second die comprises a decimator comprising a multiplexer, coupled to the parallel lanes, that outputs n bits sequentially received on any one selected lane.

16. The integrated circuit of claim 15 , wherein the decimator comprises a serial-to-parallel converter, coupled to the multiplexer and the PRBS checker, that receives n serial bits from the multiplexer and output the n bits in parallel to the PRBS checker.