Controller, memory system and operating method thereof
An operating method of a controller, the operating method comprising: reading first data stored in a first read group selected among read groups of a memory device when a sudden power off (SPO) occurs and then power is on; identifying the number of error bit data in each of the first data; and performing a reclaim operation to each of the first data based on the number of error bit data in each of the first data.
1. An operating method of a controller, the operating method comprising:
reading first data stored in a first read group selected among read groups of a memory device when a sudden power off (SPO) occurs and then power is on;
determining the number of error bit data in each of the first data; and
performing a reclaim operation to each of the first data based on the number of error bit data in each of the first data,
wherein the first read group is selected among the read group according to a round robin scheme.
2. The operating method of claim 1 , wherein each of the read groups includes a predetermined number of word lines, and
wherein the first read group is selected among the read groups based on an occurrence number of the SPO.
3. The operating method of claim 1 , wherein the reclaim operation is performed to second data having a smaller number of error bit data than a predetermined threshold among the first data.
4. The operating method of claim 3 , wherein the predetermined threshold is between one (1) and the number of correctable error bit data.
5. The operating method of claim 1 , wherein each of the read groups includes word lines of different memory dies in the memory device.
6. An operating method of a controller, the method comprising:
reading first data stored in a first read group selected among read groups of a memory device when a sudden power off (SPO) occurs and then power is on;
identifying the number of error bit data in each of the first data; and
performing a reclaim operation to each of the first data based on the number of error bit data in each of the first data,
wherein each of the read groups includes a predetermined number of word lines, and
wherein the first read group is selected among the read groups based on an occurrence number of the SPO.
7. A controller comprising:
an error correction code unit configured to determine the number of error bit data in each of first data;
a processor configured to:
read the first data stored in a first read group selected among read groups of a memory device when a sudden power off (SPO) occurs and then power is on; and
perform a reclaim operation to each of the first data based on the number of error bit data in each of the first data,
wherein the processor is configured to select the first read group among the read group according to a round robin scheme.
8. The controller of claim 7 , wherein each of the read groups includes a predetermined number of word lines.
9. The controller of claim 8 , wherein the processor is configured to select the first read group among the read groups based on an occurrence number of the SPO.
10. The controller of claim 7 , wherein the processor is configured to perform the reclaim operation to second data having a smaller number of error bit data than a predetermined threshold among the first data.
11. The controller of claim 10 , wherein the predetermined threshold is between one (1) and the number of correctable error bit data.
12. The controller of claim 7 , wherein each of the read groups includes word lines of different memory dies in the memory device.
13. A memory system comprising:
a memory device suitable for storing data; and
a controller suitable for controlling the memory device,
wherein the controller configured to:
read first data stored in a first read group selected among read groups of the memory device when a sudden power off (SPO) occurs and then power is on;
determine the number of error bit data in each of the first data; and
perform a reclaim operation to each of the first data based on the number of error bit data in each of the first data,
wherein the controller is configured to select the first read group among the read group according to a round robin scheme.
14. The memory system of claim 13 , wherein each of the read groups includes a predetermined number of word lines.
15. The memory system of claim 14 , wherein the controller is configured to select the first read group among the read groups based on an occurrence number of the SPO.
16. The memory system of claim 13 , wherein the controller is configured to perform the reclaim operation to second data having a smaller number of error bit data than a predetermined threshold among the first data.
17. The memory system of claim 16 , wherein the predetermined threshold is between one (1) and the number of correctable error bit data.