Memory device and operating method thereof

1. A method of operating a memory device including a plurality of memory cell strings each including a plurality of memory cells coupled between a common source line and a bit line, a source selection line coupled between the common source line and the plurality of memory cells, and a drain selection line coupled between the bit line and the plurality of memory cells, the method comprising:

matching a voltage of a selected word line, among word lines coupled to the plurality of memory cells, with a voltage of unselected word lines; and

precharging a channel region of the plurality of memory cell strings through the common source line while discharging the selected word line and the unselected word lines.

2. The method of claim 1 , wherein the matching of the voltages comprises:

applying an equalizing voltage to the selected word line, the equalizing voltage having a same level as a voltage applied to the unselected word lines; and

discharging a drain selection line of a selected memory cell string, among the plurality of memory cell strings.

3. The method of claim 2 , wherein the equalizing voltage turns on memory cells coupled to the unselected word lines.

4. The method of claim 2 , wherein the matching of the voltages further comprises applying a control voltage to a source selection line of the selected memory cell string.

5. The method of claim 4 , wherein the control voltage has a minimum voltage level by which a source selection transistor coupled to unselected memory cell strings, among the plurality of memory cell strings, is turned on to transfer a precharge voltage applied through the common source line to the channel region of the plurality of memory cell strings.

6. The method of claim 1 , wherein the precharging of the channel region comprises:

applying a first discharge voltage to the selected word line and applying a second discharge voltage to a first unselected word line group located between the selected word line and the drain selection line, among the unselected word lines; and

applying a ground voltage to a second unselected word line group including unselected word lines located between the selected word line and the source selection line while applying the first discharge voltage and the second discharge voltage.

7. The method of claim 6 , wherein the precharging of the channel region further comprises applying a control voltage to a source selection line of unselected memory cell strings, among the plurality of memory cell strings, for a predetermined reference time, while the first discharge voltage and the second discharge voltage are applied to the selected word line and the first unselected word line group, respectively.

8. The method of claim 7 , wherein the first discharge voltage has a greater voltage level than the second discharge voltage.

9. The method of claim 7 , wherein the control voltage has a greater voltage level than the first discharge voltage.

10. The method of claim 6 , wherein the precharging of the channel region further comprises applying a precharge voltage to the common source line while applying a control voltage to the source selection line of the unselected memory cell strings.

11. The method of claim 10 , wherein the second discharge voltage has a minimum voltage level by which the precharge voltage is transferred to the channel region.

12. The method of claim 10 , wherein the precharging of the channel region further comprises setting a bit line voltage according to data to be stored in memory cells coupled to the selected word line while applying the precharge voltage to the common source line.

13. The method of claim 1 , wherein the precharging of the channel region further comprises:

applying a first discharge voltage to the selected word line and applying a ground voltage to the unselected word lines;

applying a control voltage to a source selection line of unselected memory cell strings, among the plurality of memory cell strings, for a predetermined reference time while applying the first discharge voltage to the selected word line; and

applying a precharge voltage to the common source line while applying the control voltage to the source selection line of the unselected memory cell strings.

14. The method of claim 1 , wherein the precharging of the channel region further comprises:

applying a first discharge voltage to the selected word line and applying a second discharge voltage to unselected word lines on which a program operation is to be performed, among the unselected word lines; and

applying a ground voltage to unselected word lines on which a program operation is performed, among the unselected word lines, while applying the first discharge voltage and the second discharge voltage.

15. The method of claim 14 , wherein the precharging of the channel region comprises:

applying a control voltage to one of a drain selection line and a source selection line of unselected memory cell strings, among the plurality of memory cell strings, for a predetermined reference time while the first discharge voltage and the second discharge voltage are applied to the selected word line and the unselected word lines on which the program operation is to be performed; and

applying a precharge voltage to one of the common source line and the bit line while applying the control voltage to one of the drain selection line and the source selection line of the unselected memory cell strings.

16. The method of claim 15 , wherein the reference time increases in length as a number of times a program voltage is applied to memory cells coupled to the selected word line increases.

17. A memory device, comprising:

a plurality of memory cell strings each including a plurality of memory cells coupled between a common source line and a bit line, a source selection line coupled between the common source line and the plurality of memory cells, and a drain selection line coupled between the bit line and the plurality of memory cells;

a peripheral circuit configured to perform a plurality of program loops including a program voltage apply step for applying a program voltage to selected memory cells, among the plurality of memory cells, and a verify step for verifying program states of the selected memory cells; and

a program operation controller configured to control the peripheral circuit to apply a precharge voltage to a channel region of the plurality of memory cell strings through the common source line or the bit line when a selected word line coupled to the selected memory cells and a plurality of unselected word lines coupled to unselected memory cells are discharged in the verify step,

wherein the unselected memory cells include all of the memory cells except for the selected memory cells.

18. The memory device of claim 17 , wherein the program operation controller comprises:

a status machine configured to generate a verify control signal for controlling the peripheral circuit to perform the verify step according to a program command input from the memory controller configured for controlling the memory device; and

a verify-related voltage controller configured to generate a verify operation signal for instructing generation of a plurality of voltages used in the verify step in response to the verify control signal.

19. The memory device of claim 18 , wherein the program operation controller further comprises a source line controller configured for controlling the precharge voltage to be applied to the common source line.

20. The memory device of claim 19 , wherein the program operation controller further comprises:

a word line control signal generator configured to control a voltage applied to the selected word line and the plurality of unselected word lines;

a selection line control signal generator configured to control voltages applied to the source selection line and the drain selection line; and

a page buffer control signal generator configured to control a voltage to be applied to the bit line.