Method for forming a semiconductor device structure comprising a gate fill metal
A method for forming a semiconductor device structure is disclosure. The method may include, depositing an NMOS gate dielectric and a PMOS gate dielectric over a semiconductor substrate, depositing a first work function metal over the NMOS gate dielectric and over the PMOS gate dielectric, removing the first work function metal over the PMOS gate dielectric, and depositing a second work function metal over the NMOS gate dielectric and over the PMOS gate dielectric. Semiconductor device structures including desired metal gate electrodes deposited by the methods of the disclosure are also disclosed.
1. A method for forming a semiconductor device structure comprising:
depositing an NMOS gate dielectric over a semiconductor substrate in a NMOS gate trench and depositing a PMOS gate dielectric over the semiconductor substrate in a PMOS gate trench;
depositing a first work function metal over the NMOS gate dielectric and over the PMOS gate dielectric;
depositing a liner layer directly onto the first work function metal;
removing the first work function metal and the liner layer over the PMOS gate dielectric; and
depositing a second work function metal over the NMOS gate dielectric and over the PMOS gate dielectric, wherein the second work function metal is deposited directly onto the liner layer in the NMOS gate trench such that the second work function metal spans a surface of the liner layer within the NMOS gate trench,
wherein depositing the second work function metal comprises filling a remainder of the PMOS gate trench and a remainder of the NMOS gate trench with the second work function metal.
2. The method of claim 1 , wherein the first work function metal comprises a metal carbide.
3. The method of claim 2 , wherein the metal carbide comprises at least one of titanium carbide, tantalum carbide, titanium aluminum carbide, or niobium aluminum carbide.
4. The method of claim 1 , further comprising depositing an additional liner layer directly over the NMOS gate dielectric and directly over the PMOS gate dielectric before depositing the first work function metal over the NMOS gate dielectric and over the PMOS gate dielectric.
5. The method of claim 4 , wherein the additional liner layer is a first liner layer and the liner layer is a second liner layer, wherein the first liner layer is a first metal nitride film, wherein the first metal nitride film comprises at least one of a first titanium nitride film, a first tantalum nitride film, or a first niobium nitride film.
6. The method of claim 5 , wherein depositing the first work function metal comprises depositing the first work function metal directly onto the first metal nitride film.
7. The method of claim 1 , wherein depositing the second work function metal comprises depositing the second work function metal directly onto the liner layer on a cap between adjacent trenches.
8. The method of claim 5 , wherein the second liner layer is a second metal nitride film, wherein the second metal nitride film comprises at least one of a second titanium nitride film, a second tantalum nitride film, or a second niobium nitride film.
9. The method of claim 8 , wherein removing the first work function metal further comprises removing the second metal nitride film.
10. The method of claim 5 , wherein removing the first work function metal further comprises removing at least a portion of the first metal nitride film.
11. The method of claim 1 , further comprising depositing a third metal nitride film over the NMOS gate dielectric and the PMOS gate dielectric.
12. The method of claim 11 , wherein the third metal nitride film comprises at least one of a third titanium nitride film, a third tantalum nitride film, or a third niobium nitride film.
13. The method of claim 1 , wherein the second work function metal comprises a molybdenum film.
14. The method of claim 13 , wherein the molybdenum film comprises a gate fill metal.
15. The method of claim 1 , wherein: depositing the first work function metal comprises depositing the first work function metal overlying sidewalls of the NMOS gate trench and overlying sidewalls of the PMOS gate trench.
16. The method of claim 1 , wherein depositing the first work function metal and the second work function metal comprises an atomic layer deposition, wherein the atomic layer deposition comprises alternately and sequentially contacting the semiconductor substrate with a molybdenum precursor and a reducing agent precursor.
17. The method of claim 16 , wherein the molybdenum precursor comprises molybdenum and a halogen.
18. The method of claim 17 , wherein the halogen comprises a chloride.
19. The method of claim 17 , wherein the molybdenum precursor further comprises a chalcogenide.
20. The method of claim 19 , wherein the chalcogenide comprises oxygen.
21. The method of claim 17 , wherein the molybdenum precursor comprises at least one of molybdenum pentachloride (MoCl 5 ) or molybdenum dichloride dioxide (MoO 2 Cl 2 ).
22. The method of claim 16 , wherein the reducing agent precursor comprises hydrogen (H 2 ).
23. The method of claim 1 , wherein the gate dielectric comprises at least one of hafnium oxide (HfO 2 ), tantalum oxide (Ta 2 O 5 ), aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO 2 ), titanium oxide (TiO 2 ), hafnium silicate (HfSiO x ) or lanthanum oxide (La 2 O 3 ).
24. The method of claim of claim 5 , wherein the thickness of the first metal nitride film is varied to enable the tuning of an effective work function of a metal gate electrode over the PMOS gate dielectric.
25. The method of claim 24 , wherein the thickness of the first metal nitride film is varied between 5 Angstroms and 30 Angstroms.
26. The method of claim 24 , wherein varying the thickness of the first metal nitride film results in a PMOS metal gate electrode with an effective work function of between approximately 4.8 eV and approximately 5.2 eV.
27. The method of claim 1 , wherein a PMOS metal gate electrode disposed over the PMOS gate dielectric comprises a metal nitride film disposed directly over the PMOS gate dielectric and a molybdenum film disposed directly over the metal nitride film.
28. The method of claim 27 , wherein the metal nitride film comprises at least one of titanium nitride, tantalum nitride, or niobium nitride.
29. The method of claim 1 , wherein a NMOS metal gate electrode disposed over the NMOS gate dielectric comprises a metal nitride film disposed directly over the NMOS gate dielectric, a first work function metal comprising a metal carbide disposed directly over the metal nitride film, an additional metal nitride film disposed directly over the first work function metal and a molybdenum film disposed directly over the additional metal nitride film.
30. The method of claim 29 , wherein the metal carbide comprises at least one of titanium carbide, tantalum carbide, titanium aluminum carbide or niobium aluminum carbide.
31. The method of claim 29 , wherein the metal nitride film comprises at least one of titanium nitride, tantalum nitride, or niobium nitride.
32. The method of claim 29 , wherein the additional metal nitride film comprises at least one of titanium nitride, tantalum nitride, or niobium nitride.
33. The method of claim 1 , wherein a PMOS metal gate electrode disposed over the PMOS gate dielectric has an effective work function of greater than 5 eV.
34. A method for forming a semiconductor device structure comprising:
depositing an NMOS gate dielectric over a semiconductor substrate in a NMOS gate trench and depositing a PMOS gate dielectric over the semiconductor substrate in a PMOS gate trench;
depositing a first work function metal over the NMOS gate dielectric and over the PMOS gate dielectric;
depositing a liner layer directly onto the first work function metal;
removing the first work function metal and the liner layer over the PMOS gate dielectric; and
depositing a second work function metal over the NMOS gate dielectric and over the PMOS gate dielectric, wherein the second work function metal is deposited directly onto the liner layer in the NMOS gate trench such that the second work function metal spans a surface of the liner layer within the NMOS gate trench,
wherein the second work function metal comprises a molybdenum film comprising a gate fill metal.
35. The method of claim 34 , wherein the first work function metal comprises a metal carbide.
36. The method of claim 35 , wherein the metal carbide comprises at least one of titanium carbide, tantalum carbide, titanium aluminum carbide, or niobium aluminum carbide.
37. The method of claim 34 , further comprising depositing an additional liner layer directly over the NMOS gate dielectric and directly over the PMOS gate dielectric before depositing the first work function metal over the NMOS gate dielectric and over the PMOS gate dielectric.
38. The method of claim 37 , wherein the additional liner layer is a first liner layer and the liner layer is a second liner layer, wherein the first liner layer is a first metal nitride film, wherein the first metal nitride film comprises at least one of a first titanium nitride film, a first tantalum nitride film, or a first niobium nitride film.
39. The method of claim 38 , wherein depositing the first work function metal comprises depositing the first work function metal directly onto the first metal nitride film.
40. The method of claim 34 , wherein depositing the second work function metal comprises depositing the second work function metal directly onto the liner layer on a cap between adjacent trenches.
41. The method of claim 38 , wherein the second liner layer is a second metal nitride film, wherein the second metal nitride film comprises at least one of a second titanium nitride film, a second tantalum nitride film, or a second niobium nitride film.
42. The method of claim 41 , wherein removing the first work function metal further comprises removing the second metal nitride film.
43. The method of claim 38 , wherein removing the first work function metal further comprises removing at least a portion of the first metal nitride film.
44. The method of claim 34 , further comprising depositing a third metal nitride film over the NMOS gate dielectric and the PMOS gate dielectric.
45. The method of claim 44 , wherein the third metal nitride film comprises at least one of a third titanium nitride film, a third tantalum nitride film, or a third niobium nitride film.
46. The method of claim 34 , wherein depositing the second work function metal comprises filling the PMOS gate trench and the NMOS gate trench with the second work function metal.
47. The method of claim 34 , wherein: depositing the first work function metal comprises depositing the first work function metal onto sidewalls of the NMOS gate trench and sidewalls of the PMOS gate trench.
48. The method of claim 34 , wherein depositing the first work function metal and the second work function metal comprises an atomic layer deposition, wherein the atomic layer deposition comprises alternately and sequentially contacting the semiconductor substrate with a molybdenum precursor and a reducing agent precursor.
49. The method of claim 48 , wherein the molybdenum precursor comprises molybdenum and a halogen.
50. The method of claim 49 , wherein the halogen comprises a chloride.
51. The method of claim 49 , wherein the molybdenum precursor further comprises a chalcogenide.
52. The method of claim 51 , wherein the chalcogenide comprises oxygen.
53. The method of claim 49 , wherein the molybdenum precursor comprises at least one of molybdenum pentachloride (MoCl 5 ) or molybdenum dichloride dioxide (MoO 2 Cl 2 ).
54. The method of claim 48 , wherein the reducing agent precursor comprises hydrogen (H 2 ).
55. The method of claim 34 , wherein the gate dielectric comprises at least one of hafnium oxide (HfO 2 ), tantalum oxide (Ta 2 O 5 ), aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO 2 ), titanium oxide (TiO 2 ), hafnium silicate (HfSiO x ) or lanthanum oxide (La 2 O 3 ).
56. The method of claim of claim 38 , wherein the thickness of the first metal nitride film is varied to enable the tuning of an effective work function of a metal gate electrode over the PMOS gate dielectric.
57. The method of claim 56 , wherein the thickness of the first metal nitride film is varied between 5 Angstroms and 30 Angstroms.
58. The method of claim 56 , wherein varying the thickness of the first metal nitride film results in a PMOS metal gate electrode with an effective work function of between approximately 4.8 eV and approximately 5.2 eV.
59. The method of claim 34 , wherein a PMOS metal gate electrode disposed over the PMOS gate dielectric comprises a metal nitride film disposed directly over the PMOS gate dielectric and a molybdenum film disposed directly over the metal nitride film.
60. The method of claim 59 , wherein the metal nitride film comprises at least one of titanium nitride, tantalum nitride, or niobium nitride.
61. The method of claim 34 , wherein a NMOS metal gate electrode disposed over the NMOS gate dielectric comprises a metal nitride film disposed directly over the NMOS gate dielectric, a first work function metal comprising a metal carbide disposed directly over the metal nitride film, an additional metal nitride film disposed directly over the first work function metal and a molybdenum film disposed directly over the additional metal nitride film.
62. The method of claim 61 , wherein the metal carbide comprises at least one of titanium carbide, tantalum carbide, titanium aluminum carbide or niobium aluminum carbide.
63. The method of claim 61 , wherein the metal nitride film comprises at least one of titanium nitride, tantalum nitride, or niobium nitride.
64. The method of claim 61 , wherein the additional metal nitride film comprises at least one of titanium nitride, tantalum nitride, or niobium nitride.
65. The method of claim 34 , wherein a PMOS metal gate electrode disposed over the PMOS gate dielectric has an effective work function of greater than 5 eV.