Memory device

1. A memory device, comprising:

a plurality of electrode layers stacked on each other in a stacking direction;

a plurality of semiconductor pillars penetrating the plurality of electrode layers in the stacking direction;

a plurality of first wirings disposed above the plurality of electrode layers in the stacking direction at a first level, each first wiring being electrically connected to at least one semiconductor pillar in the plurality of semiconductor pillars; and

a second wiring disposed above the plurality of electrode layers in the stacking direction at the first level, the second wiring being insulated from the plurality of semiconductor pillars, wherein

the second wiring and the plurality of first wirings extend in parallel along a first direction intersecting the stacking direction and are spaced from each other in a second direction intersecting the first and stacking directions,

a width of the second wiring in the second direction is equal to a width of each first wiring in the plurality of first wirings in the second direction, and

a spacing distance along the second direction between the second wiring and a nearest first wiring in the plurality of first wirings is greater than a spacing interval along the second direction between adjacent first wirings.

2. The memory device according to claim 1 , wherein the second wiring is disposed above at least one semiconductor pillar in the plurality of semiconductor pillars.

3. The memory device according to claim 1 , wherein

the spacing interval is substantially equal to the width of each first wiring, and

the spacing distance is equal to five times the spacing interval.

4. The memory device according to claim 1 , wherein the plurality of first wirings are bit line wirings and the second wiring is a dummy bit line wiring.

5. The memory device according to claim 1 , further comprising:

a source line layer disposed under the plurality of electrode layers in the stacking direction; and

a third wiring disposed above the plurality of electrode layers in the stacking direction and electrically connected to the source line layer, wherein

the second wiring is between the plurality of first wirings and the third wiring in the second direction.

6. The memory device according to claim 5 , wherein the third wiring is a shunt wiring.

7. The memory device according to claim 1 , further comprising:

an interlayer insulating film between the plurality of electrode layers and the first wirings and between the plurality of electrode layers and the second wiring, wherein

the second wiring is electrically insulated from the plurality of semiconductor pillars by the interlayer insulating film.

8. The memory device according to claim 1 , wherein the plurality of first wirings are electrically connected to the plurality of semiconductor pillars via connection plugs extending through an interlayer insulating film in the stacking direction.

9. The memory device according to claim 1 , wherein at least one semiconductor pillar in the plurality of semiconductor pillars is covered with a memory film.

10. The memory device according to claim 1 , wherein the second wiring is electrically floating and only insulating material is disposed between the second wiring and the nearest first wiring.

11. A memory device, comprising:

a source line layer;

a plurality of word line layers stacked on the source line in a stacking direction;

a plurality of memory holes penetrating the plurality of word line layers in the stacking direction and reaching the source line layer, each memory hole including a semiconductor pillar covered with a memory film;

a plurality of bit line wirings disposed above the plurality of word line layers in the stacking direction at a first level, each bit line wiring being electrically connected to at least one semiconductor pillar in the plurality of memory holes; and

a dummy bit line wiring disposed above the plurality of word line layers in the stacking direction at the first level, the dummy bit line wiring being electrically insulated from the plurality of memory holes, wherein

the dummy bit line wiring and the plurality of bit line wirings extend in parallel along a first direction intersecting the stacking direction and are spaced from each other in a second direction intersecting the first and stacking directions,

a width of the dummy bit line wiring in the second direction is equal to a width of each bit line wirings in the plurality of bit line wirings in the second direction, and

a spacing distance along the second direction between the dummy bit line wiring and a nearest bit line wiring in the plurality of bit line wirings is greater than a spacing interval along the second direction between adjacent bit line wirings in the plurality of bit line wirings.

12. The memory device according to claim 11 , wherein the spacing interval is substantially equal to the width of each bit line wiring, and the spacing distance is substantially equal to five times the spacing interval.

13. The memory device according to claim 11 , further comprising:

a shunt wiring disposed above the plurality of word line layers in the stacking direction at the first level and electrically connected to the source line layer, wherein

the dummy bit line wiring is between the shunt wiring and plurality of bit line wirings in the second direction.

14. The memory device according to claim 13 , wherein the spacing interval is substantially equal to the width of each bit line wiring, and the spacing distance is substantially equal to five times the spacing interval.