IP Library Granted Patent US 10,607,962
Granted Patent B2
US 10,607,962 · App. 15/751,984 · Granted Mar 31, 2020

Method for manufacturing semiconductor chips

Inventors: Frank Osterwald (Kiel, DE); Martin Becker (Kiel, DE); Holger Ulrich (Eisendorf, DE); Ronald Eisele (Surendorf, DE); Jacek Rudzki (Kiel, DE)
Assignee: DANFOSS SILICON POWER GMBH
H01L24/94H01L24/92H01L24/97H01L2224/291H01L2224/32225H01L2224/48491H01L2224/83002H01L2224/8384H01L2224/83447H01L2224/83986H01L2224/9221H01L2224/9222H01L2224/94H01L2224/97
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,607,962
App. No.
15/751,984
Granted
Mar 31, 2020
Kind
B2
Abstract

A method for manufacturing semiconductor chips ( 2, 3 ) having arranged thereon metallic shaped bodies ( 6 ), having the following steps: arranging a plurality of metallic shaped bodies ( 6 ) on a processed semiconductor wafer while forming a layer arranged between the semiconductor wafer and the metallic shaped bodies ( 6 ), exhibiting a first connection material ( 4 ) and a second connection material ( 5 ), and processing the first connection material ( 4 ) for connecting the metallic shaped bodies ( 6 ) to the semiconductor wafer without processing the second connecting material ( 5 ), wherein the semiconductor chips ( 2, 3 ) are separated either prior to arranging the metallic shaped bodies ( 6 ) on the semiconductor wafer or after processing the first connection material ( 4 ).

Claims (29)

1. A method for manufacturing semiconductor chips having arranged thereon metallic shaped bodies, having the following steps:

arranging a plurality of metallic shaped bodies on a processed semiconductor wafer while forming a layer arranged between the semiconductor wafer and the metallic shaped body, exhibiting a first connection material and a second connection material, and

processing the first connection material for connecting the metallic shaped bodies to the semiconductor wafer without processing the second connecting material,

wherein the semiconductor chips are separated either prior to arranging the metallic shaped bodies on the semiconductor wafer or after processing the first connection material.

2. The method according to claim 1 , wherein

the first connection material is an adhesive and the second connection material is a solder material or a sintering material

or

the first connection material is a solder material and the second connection material is a sintering material.

3. The method according to claim 2 , wherein separating the semiconductor chips takes place prior to arranging the metallic shaped bodies on the processed semiconductor wafer using a wet cutting method.

4. The method according to claim 2 , wherein separating the semiconductor chips takes place after processing the first connection material using a dry cutting method.

5. A method for manufacturing a semiconductor module exhibiting a substrate and a semiconductor chip having arranged thereon a metallic shaped body, having the following steps:

manufacturing a semiconductor chip having arranged thereon a metallic shaped body according to claim 2 ,

arranging the semiconductor chip on the substrate while forming a layer of a third connection material arranged between the semiconductor chip and the substrate, and

processing the layer arranged between the semiconductor chip on the substrate and the layer arranged between the metallic shaped body and the semiconductor chip in one step.

6. The method according to claim 1 , wherein separating the semiconductor chips takes place prior to arranging the metallic shaped bodies on the processed semiconductor wafer using a wet cutting method.

7. A method for manufacturing a semiconductor module exhibiting a substrate and a semiconductor chip having arranged thereon a metallic shaped body , having the following steps:

manufacturing a semiconductor chip having arranged thereon a metallic shaped body according to claim 6 ,

arranging the semiconductor chip on the substrate while forming a layer of a third connection material arranged between the semiconductor chip and the substrate, and

processing the layer arranged between the semiconductor chip on the substrate and the layer arranged between the metallic shaped body and the semiconductor chip in one step.

8. The method according to claim 1 , wherein separating the semiconductor chips takes place after processing the first connection material using a dry cutting method.

9. A method for manufacturing a semiconductor module exhibiting a substrate and a semiconductor chip having arranged thereon a metallic shaped body , having the following steps:

manufacturing a semiconductor chip having arranged thereon a metallic shaped body according to claim 8 ,

arranging the semiconductor chip on the substrate while forming a layer of a third connection material arranged between the semiconductor chip and the substrate, and

processing the layer arranged between the semiconductor chip on the substrate and the layer arranged between the metallic shaped body and the semiconductor chip in one step.

10. A method for manufacturing a semiconductor module exhibiting a substrate and a semiconductor chip having arranged thereon a metallic shaped body, having the following steps:

manufacturing a semiconductor chip having arranged thereon a metallic shaped body according to claim 1 ,

arranging the semiconductor chip on the substrate while forming a layer of a third connection material arranged between the semiconductor chip and the substrate, and

processing the layer arranged between the semiconductor chip and the substrate and the layer arranged between the metallic shaped body and the semiconductor chip in one step.

11. The method according to claim 10 , wherein the second connection material and the third connection material are identical.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 26, 2018
From: OSTERWALD, FRANK; BECKER, MARTIN; ULRICH, HOLGER; EISELE, RONALD; RUDZKI, JACEK
To: DANFOSS SILICON POWER GMBH
Reel/Frame 046202/0935 →
Priority Claims (1)
DE 10 2015 113 421 · Aug 14, 2015 · national
Continuity (1)
Related Publication 20180240776A1 · Aug 23, 2018