Layout pattern for static random access memory

1. A static random access memory (SRAM) layout pattern, comprising:

a substrate;

two SRAM cells are disposed on the substrate, disposed in a first region and a second region adjacent to the first region respectively, wherein each SRAM cell includes a first inverter and a second inverter coupling with each other and constituting a latch circuit, wherein the first inverter includes a first pull-up transistor (PU 1 ) and a first pull-down transistor (PD 1 ), the second inverter includes a second pull-up transistor (PU 2 ) and a second pull-down transistor (PD 2 );

a dummy layer crossing the first region and the second region, and located between the PD 1 in the first region and the PD 1 in the second region; and

a contact structure disposed on the dummy layer and electrically connected to a voltage source Vss.

2. The static random access memory layout pattern of claim 1 , wherein the PD 1 in the first region comprises a first gate, a gate length of the first gate is defined as L 1 , and a length of the dummy layer is defined as L 2 , wherein L 2 /L 1 is larger than 10.

3. The static random access memory layout pattern of claim 1 , further comprising a first structural layer, wherein in the first region, the PU 1 , the PD 1 , the PU 2 , the PD 2 , and the dummy layer are located in the first structural layer.

4. The static random access memory layout pattern of claim 3 , further comprising a first metal trace electrically connecting the contact structure and the voltage source Vss, and the first metal trace is located in a second structural layer (M 1 ), and the second structural layer is located on the first structural layer.

5. The static random access memory layout pattern of claim 1 , wherein the dummy layer is located on a fin structure, and the fin structure comprises a first portion located in the first region and a second portion located in the second region.

6. The static random access memory layout pattern of claim 5 , further comprising a stress layer disposed under the dummy layer, and the stress layer is located between the first portion and the second portion.

7. The static random access memory layout pattern of claim 6 , wherein the stress layer provides a stress to the PD 1 in the first region and to the PD 1 in the second region.

8. The static random access memory layout pattern of claim 1 , wherein each of the SRAM cells further comprises a first access transistor (PG 1 A), a second access transistor (PG 1 B), a third access transistor (PG 2 A) and a fourth access transistor (PG 2 B), electrically connected to the latch circuit respectively.

9. The static random access memory layout pattern of claim 8 , wherein when viewed in a top view, the PG 1 A comprises a second gate layer, the PU 2 comprises a third gate layer, and one side of the second gate layer, one side of the third gate layer, and one side of the dummy layer are aligned with each other.

10. The static random access memory layout pattern of claim 1 , wherein each of the SRAM cells is an eight transistors dual-port static random access memory (8T-dual port SRAM).

11. The static random access memory layout pattern of claim 1 , wherein the dummy layer is an integrally formed structure.

12. A static random access memory (SRAM) layout pattern, comprising:

a substrate;

two SRAM cells are disposed on the substrate, disposed in a first region and a second region adjacent to the first region respectively, wherein each SRAM cell includes a first inverter and a second inverter coupling with each other and constituting a latch circuit, wherein the first inverter includes a first pull-up transistor (PU 1 ) and a first pull-down transistor (PD 1 ), the second inverter includes a second pull-up transistor (PU 2 ) and a second pull-down transistor (PD 2 );

a first dummy gate layer located in the first region and crossing over a first fin structure;

a second dummy gate layer located in the second region adjacent to the first dummy gate layer and crossing over a second fin structure, wherein the first fin structure directly contacts the second fin structure; and

a contact structure disposed on the first dummy layer and electrically connected to a voltage source Vss.

13. The static random access memory layout pattern of claim 12 , further comprising a first structural layer, wherein in the first region, the PU 1 , the PD 1 , the PU 2 , the PD 2 , and the dummy layer are located in the first structural layer.

14. The static random access memory layout pattern of claim 13 , further comprising a first metal trace electrically connecting the contact structure and the voltage source Vss, and the first metal trace is located in a second structural layer (M 1 ), and the second structural layer is located on the first structural layer.

15. The static random access memory layout pattern of claim 12 , wherein when viewed in a cross section view, a top surface of the first fin structure is aligned with a top surface of the second fin structure.

16. The static random access memory layout pattern of claim 12 , wherein each of the SRAM cells further comprises a first access transistor (PG 1 A), a second access transistor (PG 1 B), a third access transistor (PG 2 A) and a fourth access transistor (PG 2 B), electrically connected to the latch circuit respectively.

17. The static random access memory layout pattern of claim 16 , wherein when viewed in a top view, the PG 1 A comprises a second gate layer, the PU 2 comprises a third gate layer, and one side of the second gate layer, one side of the third gate layer, and one side of the dummy gate layer are aligned with each other.

18. The static random access memory layout pattern of claim 12 , wherein each of the SRAM cells is an eight transistors dual-port static random access memory (8T-dual port SRAM).