Integrated two-terminal device with logic device for embedded application
Devices and methods of forming a device. A two-terminal device element includes a device stack coupled between first and second terminals. The first terminal contacts a metal line in an underlying interconnect level, and the second terminal is formed over the device layer. An encapsulation liner covers exposed side surfaces of the device stack of the two-terminal device element. A dual damascene interconnect is coupled to the two-terminal device element.
1. A device comprising:
a substrate;
an interconnect level including a first dielectric layer over the substrate and a first metal line in the first dielectric layer;
an etch stop layer over the first dielectric layer, the etch stop layer including a trench opening that exposes the first metal line;
a magnetic random access memory cell including a storage element over the first dielectric layer, the storage element including a bottom electrode in the trench opening and in direct contact with the first metal line, a device stack on the bottom electrode, and a top electrode on the device stack, the device stack having side surfaces, and the bottom electrode extending beyond the side surfaces of the device stack;
an encapsulation liner located on the side surfaces of the device stack; and
a second dielectric layer including a dual damascene interconnect coupled to the top electrode of the storage element.
2. The device of claim 1 wherein the device stack comprises a magnetic tunneling junction element that includes a fixed layer, one or more tunneling barrier layers, and a free layer.
3. The device of claim 1 wherein the first dielectric layer and the second dielectric layer comprise a low-k dielectric material.
4. The device of claim 1 wherein the top electrode has side surfaces over the side surfaces of the device stack, and the encapsulation liner is located on the side surfaces of the top electrode.
5. The device of claim 4 wherein the dual damascene interconnect includes a second metal line and a via contact coupling the second metal line to the top electrode, the via contact has a bottom in contact with the top electrode, and the encapsulation liner extends above the side surfaces of the top electrode.
6. The device of claim 5 wherein the top electrode and the device stack have a first width dimension, and the via contact has a second width dimension that is less than or equal to the first width dimension.
7. The device of claim 4 wherein the dual damascene interconnect includes a second metal line and a via contact coupling the second metal line to the top electrode, the via contact has a bottom in contact with the top electrode, and the encapsulation liner surrounds the bottom of the via contact.
8. The device of claim 7 wherein the top electrode and the device stack have a first width dimension, and the via contact has a second width dimension that is less than or equal to the first width dimension.
9. The device of claim 1 further comprising:
a third dielectric layer located between the etch stop layer and the second dielectric layer, the trench opening further extending through the third dielectric layer, the bottom electrode in the trench opening surrounded by the third dielectric layer, the third dielectric layer having a top surface, and the encapsulation liner further located on the top surface of the third dielectric layer between the third dielectric layer and the second dielectric layer.
10. The device of claim 9 wherein the bottom electrode has a top surface coplanar with the top surface of the third dielectric layer.
11. The device of claim 1 further comprising:
a third dielectric layer located between the etch stop layer and the second dielectric layer, the trench opening further extending through the third dielectric layer, the bottom electrode in the trench opening surrounded by the third dielectric layer, the third dielectric layer having a top surface, and the second dielectric layer is in direct contact with the top surface of the third dielectric layer.
12. The device of claim 11 wherein the bottom electrode has a top surface coplanar with the top surface of the third dielectric layer.
13. The device of claim 1 wherein the encapsulation liner fully covers the side surfaces of the device stack.
14. The device of claim 13 wherein the top electrode has side surfaces over the side surfaces of the device stack, and the encapsulation liner is located on the side surfaces of the top electrode.
15. The device of claim 14 wherein the encapsulation liner fully covers the side surfaces of the top electrode.
16. The device of claim 1 wherein the magnetic random access memory cell further includes a transistor coupled to the first metal line of the interconnect level.