Nanosheet isolated source/drain epitaxy by surface treatment and incubation delay
A semiconductor device includes a plurality of stacked structures spaced apart from each other on a substrate, wherein the plurality of stacked structures each comprise a plurality of gate layers and a plurality of channel layers, a plurality of arsenic implanted regions on portions of a surface of the substrate adjacent the plurality of stacked structures, and a plurality of epitaxial source/drain regions extending from the plurality of stacked structures, wherein the plurality of epitaxial source/drain regions are spaced apart from the plurality of arsenic implanted regions.
1. A semiconductor device, comprising:
a plurality of stacked structures spaced apart from each other on a substrate, wherein the plurality of stacked structures each comprise a plurality of gate layers and a plurality of channel layers;
a plurality of arsenic implanted regions on portions of a surface of the substrate adjacent the plurality of stacked structures; and
a plurality of epitaxial source/drain regions extending from the plurality of stacked structures, wherein the plurality of epitaxial source/drain regions are spaced apart from the plurality of arsenic implanted regions;
wherein at least part of the arsenic implanted regions are formed in a recessed portion of the substrate.
2. A semiconductor device, comprising:
a plurality of stacked structures spaced apart from each other on a substrate, wherein the plurality of stacked structures each comprise a plurality of gate layers and a plurality of channel layers;
a plurality of arsenic implanted regions on portions of a surface of the substrate adjacent the plurality of stacked structures;
a plurality of epitaxial source/drain regions extending from the plurality of stacked structures, wherein the plurality of epitaxial source/drain regions are spaced apart from the plurality of arsenic implanted regions; and
an inter-layer dielectric layer filling in a plurality of spaces between the plurality of epitaxial source/drain regions and the plurality of arsenic implanted regions.
3. The semiconductor device according to claim 1 , wherein the plurality of epitaxial source/drain regions extend from lateral sides of the plurality of channel layers.
4. The semiconductor device according to claim 1 , further comprising a plurality of gate dielectric layers respectively disposed around the plurality of gate layers.
5. The semiconductor device according to claim 4 , further comprising a plurality of dielectric layers respectively disposed adjacent the plurality of gate dielectric layers in the plurality of stacked structures.
6. The semiconductor device according to claim 5 , wherein the plurality of dielectric layers are disposed between adjacent ones of the plurality of epitaxial source/drain regions and adjacent ones of the plurality of gate dielectric layers.
7. The semiconductor device according to claim 5 , wherein the plurality of dielectric layers comprise a nitride.
8. The semiconductor device according to claim 6 , wherein the plurality of gate dielectric layers comprise a high-K dielectric material.
9. A semiconductor device, comprising:
a plurality of stacked semiconductor structures spaced apart from each other on a substrate;
a plurality of arsenic implanted regions on portions of a surface of the substrate adjacent the plurality of stacked semiconductor structures; and
a plurality of epitaxial source/drain regions extending from the plurality of stacked semiconductor structures, wherein the plurality of epitaxial source/drain regions are spaced apart from the plurality of arsenic implanted regions;
wherein at least part of the arsenic implanted regions are formed in a recessed portion of the substrate.
10. A semiconductor device, comprising:
a plurality of stacked semiconductor structures spaced apart from each other on a substrate;
a plurality of arsenic implanted regions on portions of a surface of the substrate adjacent the plurality of stacked semiconductor structures;
a plurality of epitaxial source/drain regions extending from the plurality of stacked semiconductor structures, wherein the plurality of epitaxial source/drain regions are spaced apart from the plurality of arsenic implanted regions; and
an inter-layer dielectric layer filling in a plurality of spaces between the plurality of epitaxial source/drain regions and the plurality of arsenic implanted regions.
11. The semiconductor device according to claim 9 , wherein the plurality of stacked semiconductor structures each comprise a plurality of channel layers.
12. The semiconductor device according to claim 11 , wherein the plurality of epitaxial source/drain regions extend from lateral sides of the plurality of channel layers.
13. The semiconductor device according to claim 9 , wherein the plurality of stacked semiconductor structures each further comprise a plurality of gate structures alternately stacked with the plurality of channel layers.
14. The semiconductor device according to claim 13 , wherein the gate structures comprise a plurality of gate dielectric layers respectively disposed around a plurality of gate layers.
15. The semiconductor device according to claim 14 , further comprising a plurality of dielectric layers respectively disposed adjacent the plurality of gate dielectric layers in the plurality of stacked semiconductor structures.
16. The semiconductor device according to claim 15 , wherein the plurality of dielectric layers are disposed between adjacent ones of the plurality of epitaxial source/drain regions and adjacent ones of the plurality of gate dielectric layers.
17. A semiconductor device, comprising:
a plurality of stacked nanosheet structures spaced apart from each other on a substrate;
a plurality of arsenic implanted regions on portions of a surface of the substrate adjacent the plurality of stacked nanosheet structures; and
a plurality of epitaxial source/drain regions extending from the plurality of stacked nanosheet structures, wherein the plurality of epitaxial source/drain regions are spaced apart from the plurality of arsenic implanted regions;
wherein at least part of the arsenic implanted regions are formed in a recessed portion of the substrate.