Rectifying element and voltage converter comprising such a rectifying element
A rectifying element includes a MOS transistor series-connected with a Schottky diode. A bias voltage is applied between the control terminal of the MOS transistor and the terminal of the Schottky diode opposite to the transistor. A pair of the rectifying elements are substituted for diodes of a rectifying bridge circuit. Alternatively, the control terminal bias is supplied from a cross-coupling against the Schottky diodes. In another implementation, the Schottky diodes are omitted and the bias voltage applied to control terminals of the MOS transistors is switched in response to cross-coupled divided source-drain voltages of the MOS transistors. The circuits form components of a power converter.
1. A circuit, comprising:
a first MOS transistor having a source coupled to a first terminal and a drain coupled to a second terminal;
a second MOS transistor having a source coupled to the first terminal and a drain coupled to a third terminal;
a first voltage divider coupled between the first and second terminals and having a first intermediate node;
a second voltage divider coupled between the first and third terminals and having a second intermediate node;
a first transistor switch coupled between a third intermediate node and a control terminal of the first MOS transistor, wherein a control terminal of the first transistor switch is coupled to the second intermediate node; and
a second transistor switch coupled between the third intermediate node and a control terminal of the second MOS transistor, wherein a control terminal of the second transistor switch is coupled to the first intermediate node.
2. The circuit of claim 1 , further comprising a voltage source configured to generate a substantially constant voltage between the third intermediate node and the first terminal.
3. The circuit of claim 1 , wherein first terminal is an anode terminal of the circuit, the second terminal is a first cathode terminal of the circuit, and the third terminal is a second cathode terminal of the circuit.
4. The circuit of claim 1 , wherein each of the first and second transistor switches is a bipolar transistor.
5. The circuit of claim 1 , wherein each of the first and second voltage dividers is a resistive voltage divider.
6. The circuit of claim 1 , wherein each of the first and second MOS transistors is of N-channel enrichment type.
7. The circuit of claim 1 , further comprising:
a first resistor coupled between the control terminal of the first MOS transistor and the source of the first MOS transistor; and
a second resistor coupled between the control terminal of the second MOS transistor and the source of the second MOS transistor.
8. The converter of claim 1 , wherein each of the first and second transistor switches is a bipolar transistor.
9. A voltage converter, comprising:
a rectifying bridge circuit comprising:
a first diode;
a first MOS transistor coupled in series with the first diode between a first terminal and a second terminal, wherein said first MOS transistor is coupled between the second terminal and a first input terminal;
a second diode;
a second MOS transistor coupled in series with the second diode between the first terminal and the second terminal, wherein said second MOS transistor is coupled between the second terminal and a second input terminal;
a first voltage divider coupled between the first input terminal and the second terminal and having a first intermediate node;
a second voltage divider coupled between the second input terminal and the second terminal and having a second intermediate node;
a first transistor switch coupled between a third intermediate node and a control terminal of the first MOS transistor, wherein a control terminal of the first transistor switch is coupled to the second intermediate node; and
a second transistor switch coupled between the third intermediate node and a control terminal of the second MOS transistor, wherein a control terminal of the second transistor switch is coupled to the first intermediate node.
10. The converter of claim 9 , wherein the second terminal is connected to an output of the converter.
11. The converter of claim 9 , further comprising:
an inductor coupled in series between the first diode and the first MOS transistor; and
a transistor switch driven by a pulse width modulation control signal and coupled between the second terminal and a series node of the series coupled inductor and first diode.
12. The converter of claim 9 , further comprising:
a first inductive element coupled in series with the first MOS transistor and the first diode, the first inductive element located between the first MOS transistor and the first diode; and
a first transistor switch driven by a pulse width modulation control signal and coupled between a first junction point and the second terminal, wherein the first junction point connects the first inductive element and the first diode.
13. The converter of claim 12 , further comprising:
a second inductive element coupled in series with the second MOS transistor and the second diode, the second inductive element located between the second MOS transistor and the second diode; and
a second transistor switch driven by a pulse width modulation control signal and coupled between a second junction point and the second terminal, wherein the second junction point connects the second inductive element and the second diode.
14. The converter of claim 9 , wherein each of the first and second voltage dividers is a resistive voltage divider.
15. The converter of claim 9 , wherein each of the first and second MOS transistors is of N-channel enrichment type.
16. The converter of claim 9 , further comprising:
a first resistor coupled between the control terminal of the first MOS transistor and the source of the first MOS transistor; and
a second resistor coupled between the control terminal of the second MOS transistor and the source of the second MOS transistor.
17. The converter of claim 9 , further comprising a voltage source configured to generate a substantially constant voltage between the third intermediate node and the second terminal.