Memory system and method of operating the same

1. A memory system comprising:

a semiconductor memory device to which an address mapping table including a plurality of map segments is stored; and

a controller configured to load and store, during a read operation, one or more map segments selected from among the plurality of map segments,

wherein the controller comprises:

a compression engine configured to compress the one or more map segments and generate one or more compressed map segments and metadata corresponding thereto;

a map data loading buffer configured to store the one or more compressed map segments and the metadata; and

a processor configured to store the one or more compressed map segments to a random access memory (RAM) using the metadata.

2. The memory system according to claim 1 , wherein the map data loading buffer comprises:

a main slot unit configured to store the one or more compressed map segments; and

a sub-slot unit configured to store the metadata.

3. The memory system according to claim 2 , wherein the main slot unit comprises a plurality of main slots, each configured to store one of the one or more compressed map segments.

4. The memory system according to claim 3 ,

wherein the sub-slot unit comprises a plurality of sub-slots respectively corresponding to the plurality of main slots, and

wherein each of the plurality of sub-slots is configured to store metadata corresponding to the compressed map segment stored in the corresponding one of the plurality of main slots.

5. The memory system according to claim 4 , wherein the metadata stored in one of the plurality of sub-slots includes information about a size of the corresponding compressed map segment.

6. The memory system according to claim 1 ,

wherein the controller further comprises the RAM configured to store the one or more compressed map segments stored in the map data loading buffer, and

wherein the processor checks sizes of the one or more compressed map segments stored in the map data loading buffer using the metadata and allocates a space corresponding to the sizes of the one or more compressed map segments to the RAM, and then copies and stores the one or more compressed map segments to the allocated space of the RAM.

7. The memory system according to claim 1 , wherein the controller further includes a decompression engine configured to decompress the one or more compressed map segments stored in the RAM and generate one or more decompressed map segments.

8. The memory system according to claim 7 , wherein the processor controls the decompression engine to select and decompress at least one compressed map segment including a logical to physical (L2P) entry corresponding to a read address, among the one or more compressed map segments stored in the RAM.

9. The memory system according to claim 7 , wherein the one or more decompressed map segments are stored to the RAM.

10. The memory system according to claim 9 , wherein the processor controls the semiconductor memory device to check a read address with reference to L2P entries of the one or more decompressed map segments and read data stored in the checked read address.

11. A memory system comprising:

a semiconductor memory device to which an address mapping table including a plurality of map segments is stored; and

a controller configured to control the semiconductor memory device to store, during a read operation, one or more compressed map segments obtained through a compression operation of compressing one or more map segments, selected from among the plurality of map segments, and metadata obtained during the compression operation, to a map data loading buffer,

wherein the metadata corresponding to the one or more compressed map segments includes information about a size of the one or more compressed map segments corresponding thereto.

12. The memory system according to claim 11 , wherein the controller comprises:

a compression engine configured to compress the selected one or more map segments and generate the one or more compressed map segments and the metadata;

a map data loading buffer configured to store the one or more compressed map segments and the metadata;

a random access memory (RAM) to which the one or more compressed map segments stored in the map data loading buffer are copied and stored; and

a processor configured to allocate a space of the RAM using the metadata, and copy and store the one or more compressed map segments to the allocated space of the RAM.

13. The memory system according to claim 11 , wherein the map data loading buffer comprises:

a main slot unit configured to store the one or more compressed map segments; and

a sub-slot unit configured to store the metadata.

14. The memory system according to claim 13 , wherein the main slot unit comprises a plurality of main slots, each configured to store one of the one or more compressed map segments.

15. The memory system according to claim 14 ,

wherein the sub-slot unit comprises a plurality of sub-slots respectively corresponding to the main slots, and

wherein each of the sub-slots is configured to store metadata corresponding to the compressed map segment stored in the corresponding one of the main slots.

16. The memory system according to claim 15 , wherein the metadata is stored in one of the plurality of sub-slots.

17. A method of operating a memory system, comprising:

loading map segments stored in a semiconductor memory device using a controller;

compressing the loaded map segments using a compression engine, generating compressed map segments and metadata respectively corresponding to the compressed map segments, and storing the compressed map segments and the metadata to a map data loading buffer; and

allocating, using a processor, a space of a random access memory (RAM) in response to the metadata, and copying and storing the compressed map segments to the allocated space.

18. The method according to claim 17 , wherein the metadata includes information about sizes of the compressed map segments.