Pre-cut plating lines on lead frames and laminate substrates for saw singulation
Described herein is a technology or a method for pre-fabricating pre-cut plating lines on a lead frame with use of a pre-cut etchback process to minimize burrs during a semiconductor package singulation process. A package includes: a chip, and a lead frame that mounts the chip. The lead frame further includes pre-fabricated pre-cut plating lines that are etched back on the lead frame to form an opening slot on a periphery of the lead frame. The opening slot allows a saw blade to cut through a prepreg material, without touching or cutting a conductive material of the lead frame.
1. A semiconductor package comprising:
a first chip mounted on a first lead frame and electrically connected to at least one first lead;
a second chip mounted on a second lead frame and electrically connected to at least one second lead;
a bonding material that attaches a backside of the first lead frame to a backside of the second lead frame, wherein each of the first and second lead frames further comprises:
a stack of prepreg material, a copper layer, and a solder mask;
a plurality of slots on a periphery of the first and second lead frames, wherein a first slot of the plurality of slots exposes a first surface of the prepreg material between an edge of the semiconductor package and the first lead and a second slot of the plurality of slots exposes a second surface of the prepreg material between the edge of the semiconductor package and the second lead.
2. The semiconductor package of claim 1 , wherein the first surface is a top surface of the prepreg material, and the second surface is a bottom surface of the prepreg material.
3. The semiconductor package of claim 1 , wherein the slot includes a half U shape.
4. The semiconductor package of claim 1 , wherein each of the plurality of slots includes sidewalls and the portion of the prepreg material exposed.
5. A device comprising:
a chip attached to a portion of a lead frame, the portion of the lead frame including a lead electrically connected to the chip, the lead frame including a prepreg material, a conductive layer, and a solder mask; wherein an edge of the device includes a portion of the prepreg material exposed in a slot between an edge of the lead and the edge of the device.
6. The device of claim 5 , wherein the slot includes a half “U” shape.
7. The device of claim 5 , wherein the slot is a pre-fabricated pre-cut plating line.
8. The device of claim 5 , wherein the slot includes a length that traverses the conductive layer on the lead frame.
9. The device of claim 5 , wherein the slot includes sidewalls and the portion of the prepreg material exposed.
10. The device of claim 5 , wherein the portion of the prepreg material exposed is top surface of the prepreg material relative to a top surface of the device.
11. The device of claim 5 , wherein the lead is electrically connected to the chip via a wire bond.
12. The device of claim 5 , wherein a width of the portion of the prepreg material exposed is the same as the width of the slot.