Semiconductor device and method for fabricating the same
The semiconductor device includes a first fin-type pattern and a second fin-type pattern which extends along a first direction; a first gate structure and a second gate structure extending in a second direction, on the first fin-type pattern and the second fin-type pattern; and a shared epitaxial pattern which connects the first fin-type pattern and the second fin-type pattern between the first gate structure and the second gate structure. An upper surface of the shared epitaxial pattern includes a first shared slope and a second shared slope which connect the first gate structure and the second gate structure, a third shared slope which is in contact with the first gate structure and connects the first shared slope and the second shared slope, and a fourth shared slope which is in contact with the second gate structure and connects the first shared slope and the second shared slope.
1. A semiconductor device comprising:
a first fin-type pattern and a second fin-type pattern which extend across a substrate along a first direction, respectively;
a first gate structure and a second gate structure which are spaced apart from each other and extend in a second direction intersecting the first direction such that the first and second fin-type patterns cross the first and second gate structures, respectively; and
a shared epitaxial pattern which connects the first fin-type pattern and the second fin-type pattern between the first gate structure and the second gate structure,
wherein the shared epitaxial pattern includes a capping epitaxial layer,
wherein an upper surface of the capping epitaxial layer includes
a first shared slope and a second shared slope which connect the first gate structure and the second gate structure,
a third shared slope which is in contact with the first gate structure and connects the first shared slope and the second shared slope, and
a fourth shared slope which is in contact with the second gate structure and connects the first shared slope and the second shared slope, and
wherein the third shared slope and the fourth shared slope meet between the first gate structure and the second gate structure to form an intersection line, which extends along the second direction such that the intersection line crosses the first and second fin type patterns.
2. The semiconductor device of claim 1 , wherein the third shared slope and the fourth shared slope have a triangular shape or a trapezoidal shape.
3. The semiconductor device of claim 1 , wherein the first shared slope and the second shared slope have a pentagonal shape or a hexagonal shape.
4. The semiconductor device of claim 1 , wherein the first shared slope, the second shared slope, the third shared slope, and the fourth shared slope have a {111} crystal surface.
5. The semiconductor device of claim 1 , further comprising:
a third fin-type pattern which extends in the first direction between the first fin-type pattern and the second fin-type pattern on the substrate,
wherein the shared epitaxial pattern connects the first fin-type pattern, the second fin-type pattern, and the third fin-type pattern.
6. The semiconductor device of claim 1 , further comprising:
a field insulating film which fills a space between the first fin-type pattern and the second fin-type pattern on the substrate; and
an air gap interposed between the shared epitaxial pattern and the field insulating film.
7. A semiconductor device comprising:
a first fin-type pattern and a second fin-type pattern on a substrate; and
a shared epitaxial pattern which connects the first fin-type pattern and the second fin-type pattern,
wherein the shared epitaxial pattern includes
a first epitaxial layer on the first fin-type pattern,
a second epitaxial layer on the second fin-type pattern,
a first connecting epitaxial layer interposed between the first epitaxial layer and the second epitaxial layer, and
a capping epitaxial layer on the first epitaxial layer, the second epitaxial layer and the first connecting epitaxial layer,
an uppermost part of the capping epitaxial layer being higher than an uppermost part of the first epitaxial layer, an uppermost part of the second epitaxial layer, and an uppermost part of the first connecting epitaxial layer.,
an upper surface of the first epitaxial layer includes a first upper slope which has a first non-zero inclination with respect to an upper surface of the substrate and is not in contact with the first connecting epitaxial layer,
an upper surface of the second epitaxial layer includes a second upper slope which has a second non-zero inclination with respect to the upper surface of the substrate and is not in contact with the first connecting epitaxial layer, and
an upper surface of the capping epitaxial layer includes a first capping slope being substantially coplanar with the first upper slope, and a second capping slope being substantially coplanar with the second upper slope.
8. The semiconductor device of claim 7 , wherein an upper surface of the first epitaxial layer includes a first upper slope which has a first non-zero inclination with respect to an upper surface of the substrate and is not in contact with the first connecting epitaxial layer,
an upper surface of the second epitaxial layer includes a second upper slope which has a second non-zero inclination with respect to the upper surface of the substrate and is not in contact with the first connecting epitaxial layer, and
an upper surface of the capping epitaxial layer includes a first capping slope extending from the first upper slope, and a second capping slope extending from the second upper slope.
9. The semiconductor device of claim 7 , wherein the first epitaxial layer and the second epitaxial layer are in contact with each other.
10. The semiconductor device of claim 7 , further comprising:
a third fin-type pattern interposed between the first fin-type pattern and the second fin-type pattern on the substrate,
wherein the shared epitaxial pattern further includes a third epitaxial layer on the third fin-type pattern, and a second connecting epitaxial layer,
the first connecting epitaxial layer connects the first epitaxial layer and the third epitaxial layer, and
the second connecting epitaxial layer connects the second epitaxial layer and the third epitaxial layer.
11. The semiconductor device of claim 7 , wherein the first epitaxial layer and the second epitaxial layer include a first substance of a first concentration, and
the first connecting epitaxial layer includes the first substance of a second concentration different from the first concentration.
12. The semiconductor device of claim 11 , wherein the capping epitaxial layer includes the first substance of a third concentration different from the second concentration.
13. The semiconductor device of claim 7 , wherein each of the first fin-type pattern and the second fin-type pattern extends along a first direction,
a first gate structure and a second gate structure spaced apart from each other and extending in a second direction intersecting with the first direction are further disposed on the first fin-type pattern and the second fin-type pattern, and
the shared epitaxial pattern connects the first fin-type pattern and the second fin-type pattern between the first gate structure and the second gate structure.